Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101203063	1			T1	111241		T2	223576		T3	109760
all_pins[1]	101203063	1			T1	111241		T2	223576		T3	109760
all_pins[2]	101203063	1			T1	111241		T2	223576		T3	109760

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	302801487	1			T1	333354		T2	670143		T3	328906
values[0x1]	807702	1			T1	369		T2	585		T3	374
transitions[0x0=>0x1]	805570	1			T1	369		T2	585		T3	374
transitions[0x1=>0x0]	805599	1			T1	369		T2	585		T3	374

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100695161	1			T1	110872		T2	222991		T3	109386
all_pins[0]	values[0x1]	507902	1			T1	369		T2	585		T3	374
all_pins[0]	transitions[0x0=>0x1]	507890	1			T1	369		T2	585		T3	374
all_pins[0]	transitions[0x1=>0x0]	7044	1			T7	59		T8	18		T9	12
all_pins[1]	values[0x0]	101196007	1			T1	111241		T2	223576		T3	109760
all_pins[1]	values[0x1]	7056	1			T7	59		T8	18		T9	12
all_pins[1]	transitions[0x0=>0x1]	6731	1			T7	59		T8	18		T9	12
all_pins[1]	transitions[0x1=>0x0]	292419	1			T7	644		T16	578		T97	862
all_pins[2]	values[0x0]	100910319	1			T1	111241		T2	223576		T3	109760
all_pins[2]	values[0x1]	292744	1			T7	644		T16	578		T97	862
all_pins[2]	transitions[0x0=>0x1]	290949	1			T7	644		T16	578		T97	862
all_pins[2]	transitions[0x1=>0x0]	506136	1			T1	369		T2	585		T3	374