Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11132681 |
1 |
|
|
T1 |
3936 |
|
T2 |
2730 |
|
T3 |
3936 |
auto[1] |
11132635 |
1 |
|
|
T1 |
3936 |
|
T2 |
2730 |
|
T3 |
3936 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
22025192 |
1 |
|
|
T1 |
7872 |
|
T2 |
5460 |
|
T3 |
7872 |
triple_byte_access |
79988 |
1 |
|
|
T13 |
78 |
|
T7 |
46 |
|
T8 |
24 |
halfword_access |
80354 |
1 |
|
|
T13 |
82 |
|
T7 |
38 |
|
T8 |
30 |
byte_access |
79782 |
1 |
|
|
T13 |
54 |
|
T7 |
40 |
|
T8 |
22 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
11012619 |
1 |
|
|
T1 |
3936 |
|
T2 |
2730 |
|
T3 |
3936 |
auto[0] |
triple_byte_access |
39994 |
1 |
|
|
T13 |
39 |
|
T7 |
23 |
|
T8 |
12 |
auto[0] |
halfword_access |
40177 |
1 |
|
|
T13 |
41 |
|
T7 |
19 |
|
T8 |
15 |
auto[0] |
byte_access |
39891 |
1 |
|
|
T13 |
27 |
|
T7 |
20 |
|
T8 |
11 |
auto[1] |
word_access |
11012573 |
1 |
|
|
T1 |
3936 |
|
T2 |
2730 |
|
T3 |
3936 |
auto[1] |
triple_byte_access |
39994 |
1 |
|
|
T13 |
39 |
|
T7 |
23 |
|
T8 |
12 |
auto[1] |
halfword_access |
40177 |
1 |
|
|
T13 |
41 |
|
T7 |
19 |
|
T8 |
15 |
auto[1] |
byte_access |
39891 |
1 |
|
|
T13 |
27 |
|
T7 |
20 |
|
T8 |
11 |