Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99685321	1			T1	27754		T2	15465		T3	1890
all_values[1]	99685321	1			T1	27754		T2	15465		T3	1890
all_values[2]	99685321	1			T1	27754		T2	15465		T3	1890

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

553681

1

T1

88

T2

285

T3

26

auto[1]

298502282

1

T1

83174

T2

46110

T3

5644

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297532284

1

T1

82518

T2

45942

T3

4881

auto[1]

1523679

1

T1

744

T2

453

T3

789

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	193670	1			T1	86		T2	281		T3	12
all_values[0]	auto[0]	auto[1]	2115	1			T1	2		T2	4		T3	4
all_values[0]	auto[1]	auto[0]	98983758	1			T1	27420		T2	15033		T3	1615
all_values[0]	auto[1]	auto[1]	505778	1			T1	246		T2	147		T3	259
all_values[1]	auto[0]	auto[0]	213813	1			T13	2		T14	4		T8	151
all_values[1]	auto[0]	auto[1]	1625	1			T13	1		T14	2		T8	9
all_values[1]	auto[1]	auto[0]	98963615	1			T1	27506		T2	15314		T3	1627
all_values[1]	auto[1]	auto[1]	506268	1			T1	248		T2	151		T3	263
all_values[2]	auto[0]	auto[0]	141023	1			T3	8		T8	4344		T34	86
all_values[2]	auto[0]	auto[1]	1435	1			T3	2		T8	27		T34	4
all_values[2]	auto[1]	auto[0]	99036405	1			T1	27506		T2	15314		T3	1619
all_values[2]	auto[1]	auto[1]	506458	1			T1	248		T2	151		T3	261