Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99685321	1			T1	27754		T2	15465		T3	1890
all_pins[1]	99685321	1			T1	27754		T2	15465		T3	1890
all_pins[2]	99685321	1			T1	27754		T2	15465		T3	1890

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	298233420	1			T1	82274		T2	45589		T3	5411
values[0x1]	822543	1			T1	988		T2	806		T3	259
transitions[0x0=>0x1]	820474	1			T1	988		T2	805		T3	259
transitions[0x1=>0x0]	820499	1			T1	988		T2	806		T3	259

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99179543	1			T1	27508		T2	15318		T3	1631
all_pins[0]	values[0x1]	505778	1			T1	246		T2	147		T3	259
all_pins[0]	transitions[0x0=>0x1]	505771	1			T1	246		T2	147		T3	259
all_pins[0]	transitions[0x1=>0x0]	4997	1			T7	10		T8	105		T9	90
all_pins[1]	values[0x0]	99680317	1			T1	27754		T2	15465		T3	1890
all_pins[1]	values[0x1]	5004	1			T7	10		T8	105		T9	90
all_pins[1]	transitions[0x0=>0x1]	4842	1			T7	10		T8	100		T9	90
all_pins[1]	transitions[0x1=>0x0]	311599	1			T1	742		T2	659		T8	3061
all_pins[2]	values[0x0]	99373560	1			T1	27012		T2	14806		T3	1890
all_pins[2]	values[0x1]	311761	1			T1	742		T2	659		T8	3066
all_pins[2]	transitions[0x0=>0x1]	309861	1			T1	742		T2	658		T8	3048
all_pins[2]	transitions[0x1=>0x0]	503903	1			T1	246		T2	147		T3	259