Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10691460 |
1 |
|
|
T1 |
29549 |
|
T2 |
17526 |
|
T3 |
6255 |
auto[1] |
10691393 |
1 |
|
|
T1 |
29549 |
|
T2 |
17526 |
|
T3 |
6255 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21144679 |
1 |
|
|
T1 |
58834 |
|
T2 |
34910 |
|
T3 |
12274 |
triple_byte_access |
79168 |
1 |
|
|
T1 |
86 |
|
T2 |
24 |
|
T3 |
78 |
halfword_access |
79644 |
1 |
|
|
T1 |
78 |
|
T2 |
54 |
|
T3 |
52 |
byte_access |
79362 |
1 |
|
|
T1 |
100 |
|
T2 |
64 |
|
T3 |
106 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10572373 |
1 |
|
|
T1 |
29417 |
|
T2 |
17455 |
|
T3 |
6137 |
auto[0] |
triple_byte_access |
39584 |
1 |
|
|
T1 |
43 |
|
T2 |
12 |
|
T3 |
39 |
auto[0] |
halfword_access |
39822 |
1 |
|
|
T1 |
39 |
|
T2 |
27 |
|
T3 |
26 |
auto[0] |
byte_access |
39681 |
1 |
|
|
T1 |
50 |
|
T2 |
32 |
|
T3 |
53 |
auto[1] |
word_access |
10572306 |
1 |
|
|
T1 |
29417 |
|
T2 |
17455 |
|
T3 |
6137 |
auto[1] |
triple_byte_access |
39584 |
1 |
|
|
T1 |
43 |
|
T2 |
12 |
|
T3 |
39 |
auto[1] |
halfword_access |
39822 |
1 |
|
|
T1 |
39 |
|
T2 |
27 |
|
T3 |
26 |
auto[1] |
byte_access |
39681 |
1 |
|
|
T1 |
50 |
|
T2 |
32 |
|
T3 |
53 |