Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
dashboard | hierarchy | modlist | groups | tests | asserts

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 287 1 T127 7 T128 4 T129 4
all_values[1] 287 1 T127 7 T128 4 T129 4
all_values[2] 287 1 T127 7 T128 4 T129 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 464 1 T127 15 T128 6 T129 6
auto[1] 397 1 T127 6 T128 6 T129 6


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 425 1 T127 11 T128 6 T129 8
auto[1] 436 1 T127 10 T128 6 T129 4


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 535 1 T127 14 T128 7 T129 9
auto[1] 326 1 T127 7 T128 5 T129 3


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 68 1 T128 2 T129 2 T170 1
all_values[0] auto[0] auto[0] auto[1] 29 1 T129 1 T170 1 T171 2
all_values[0] auto[0] auto[1] auto[0] 64 1 T170 1 T171 1 T172 2
all_values[0] auto[0] auto[1] auto[1] 23 1 T127 2 T128 1 T167 2
all_values[0] auto[1] auto[0] auto[1] 57 1 T127 3 T170 1 T167 3
all_values[0] auto[1] auto[1] auto[1] 46 1 T127 2 T128 1 T129 1
all_values[1] auto[0] auto[0] auto[0] 94 1 T127 6 T128 2 T170 1
all_values[1] auto[0] auto[1] auto[0] 81 1 T129 3 T170 2 T167 1
all_values[1] auto[1] auto[0] auto[1] 60 1 T129 1 T170 1 T167 1
all_values[1] auto[1] auto[1] auto[1] 52 1 T127 1 T128 2 T167 2
all_values[2] auto[0] auto[0] auto[0] 65 1 T127 5 T129 1 T170 2
all_values[2] auto[0] auto[0] auto[1] 28 1 T127 1 T167 1 T171 1
all_values[2] auto[0] auto[1] auto[0] 53 1 T128 2 T129 2 T172 2
all_values[2] auto[0] auto[1] auto[1] 30 1 T170 1 T172 1 T173 1
all_values[2] auto[1] auto[0] auto[1] 63 1 T128 2 T129 1 T170 1
all_values[2] auto[1] auto[1] auto[1] 48 1 T127 1 T167 3 T172 2


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%