Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99323213	1			T1	572634		T4	183765		T5	157832
all_values[1]	99323213	1			T1	572634		T4	183765		T5	157832
all_values[2]	99323213	1			T1	572634		T4	183765		T5	157832

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

505518

1

T1

14

T4

2354

T13

3

auto[1]

297464121

1

T1

171788

T4

548941

T5

473496

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

296439297

1

T1

170739

T4

550758

T5

472044

auto[1]

1530342

1

T1

10509

T4

537

T5

1452

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	187950	1			T6	1		T7	428		T8	4539
all_values[0]	auto[0]	auto[1]	2071	1			T6	2		T7	6		T8	20
all_values[0]	auto[1]	auto[0]	98625149	1			T1	569131		T4	183586		T5	157348
all_values[0]	auto[1]	auto[1]	508043	1			T1	3503		T4	179		T5	484
all_values[1]	auto[0]	auto[0]	139905	1			T1	5		T13	2		T14	11
all_values[1]	auto[0]	auto[1]	1562	1			T1	2		T13	1		T14	5
all_values[1]	auto[1]	auto[0]	98673194	1			T1	569126		T4	183586		T5	157348
all_values[1]	auto[1]	auto[1]	508552	1			T1	3501		T4	179		T5	484
all_values[2]	auto[0]	auto[0]	172502	1			T1	5		T4	2353		T6	11
all_values[2]	auto[0]	auto[1]	1528	1			T1	2		T4	1		T6	6
all_values[2]	auto[1]	auto[0]	98640597	1			T1	569126		T4	181233		T5	157348
all_values[2]	auto[1]	auto[1]	508586	1			T1	3501		T4	178		T5	484