Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
348972 |
1 |
|
|
T1 |
2 |
|
T4 |
244 |
|
T5 |
620 |
auto[1] |
345796 |
1 |
|
|
T1 |
4672 |
|
T13 |
4672 |
|
T14 |
778 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173740 |
1 |
|
|
T1 |
1216 |
|
T4 |
64 |
|
T5 |
165 |
lower_val |
172636 |
1 |
|
|
T1 |
1169 |
|
T4 |
62 |
|
T5 |
150 |
zero_val |
1780 |
1 |
|
|
T1 |
9 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
260402 |
1 |
|
|
T1 |
1168 |
|
T4 |
142 |
|
T5 |
336 |
lower_val |
260626 |
1 |
|
|
T1 |
1168 |
|
T4 |
102 |
|
T5 |
284 |
zero_val |
173740 |
1 |
|
|
T1 |
2338 |
|
T12 |
2 |
|
T13 |
2384 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43593 |
1 |
|
|
T4 |
37 |
|
T5 |
85 |
|
T6 |
116 |
higher_val |
higher_val |
auto[1] |
21498 |
1 |
|
|
T1 |
304 |
|
T13 |
315 |
|
T14 |
45 |
higher_val |
lower_val |
auto[0] |
43589 |
1 |
|
|
T4 |
27 |
|
T5 |
80 |
|
T6 |
92 |
higher_val |
lower_val |
auto[1] |
21733 |
1 |
|
|
T1 |
300 |
|
T13 |
306 |
|
T14 |
48 |
higher_val |
zero_val |
auto[0] |
92 |
1 |
|
|
T48 |
1 |
|
T36 |
1 |
|
T56 |
1 |
higher_val |
zero_val |
auto[1] |
43235 |
1 |
|
|
T1 |
612 |
|
T13 |
605 |
|
T14 |
107 |
lower_val |
higher_val |
auto[0] |
43409 |
1 |
|
|
T4 |
40 |
|
T5 |
90 |
|
T6 |
91 |
lower_val |
higher_val |
auto[1] |
21245 |
1 |
|
|
T1 |
293 |
|
T13 |
265 |
|
T14 |
37 |
lower_val |
lower_val |
auto[0] |
43611 |
1 |
|
|
T1 |
1 |
|
T4 |
22 |
|
T5 |
60 |
lower_val |
lower_val |
auto[1] |
21229 |
1 |
|
|
T1 |
283 |
|
T13 |
280 |
|
T14 |
49 |
lower_val |
zero_val |
auto[0] |
74 |
1 |
|
|
T7 |
1 |
|
T11 |
2 |
|
T123 |
1 |
lower_val |
zero_val |
auto[1] |
43068 |
1 |
|
|
T1 |
592 |
|
T13 |
586 |
|
T14 |
91 |
zero_val |
higher_val |
auto[0] |
544 |
1 |
|
|
T6 |
3 |
|
T7 |
1 |
|
T8 |
5 |
zero_val |
higher_val |
auto[1] |
133 |
1 |
|
|
T1 |
4 |
|
T7 |
2 |
|
T11 |
1 |
zero_val |
lower_val |
auto[0] |
525 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
1 |
zero_val |
lower_val |
auto[1] |
123 |
1 |
|
|
T1 |
1 |
|
T7 |
1 |
|
T36 |
1 |
zero_val |
zero_val |
auto[0] |
266 |
1 |
|
|
T12 |
1 |
|
T13 |
1 |
|
T14 |
1 |
zero_val |
zero_val |
auto[1] |
189 |
1 |
|
|
T1 |
3 |
|
T13 |
4 |
|
T7 |
3 |