Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hash_mode	3	0	3	100.00	100	1	1	0
kmac_mode	2	0	2	100.00	100	1	1	2
msgfifo_depth	11	0	11	100.00	100	1	1	0
msgfifo_empty	2	0	2	100.00	100	1	1	2
msgfifo_full	2	0	2	100.00	100	1	1	2

Summary for Variable hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	16720580	1			T4	151433		T7	133297		T8	138384
shake	57837015	1			T1	567959		T4	51498		T13	567271
sha3	35066867	1			T4	933		T5	157211		T14	227479

---

Summary for Variable kmac_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

92902794

1

T1

567959

T4

52431

T5

157211

auto[1]

16721668

1

T4

151433

T7

133296

T8

138399

---

Summary for Variable msgfifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for msgfifo_depth

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
depth[0x00]	91127414	1			T1	556337		T4	155684		T5	102255
depth[0x01]	3919813	1			T1	11564		T4	9923		T5	11811
depth[0x02]	3533562	1			T1	58		T4	10522		T5	12878
depth[0x03]	3313696	1			T4	10155		T5	12213		T13	26272
depth[0x04]	2964262	1			T4	8986		T5	11919		T13	22990
depth[0x05]	1746299	1			T4	5086		T5	6134		T13	10584
depth[0x06]	617859	1			T4	1247		T5	1		T13	4
depth[0x07]	512669	1			T4	191		T7	2		T8	4
depth[0x08]	503913	1			T4	258		T7	5		T8	6
depth[0x09]	478892	1			T4	168		T7	22		T8	45
depth[0x0a]	906083	1			T4	1644		T7	90		T8	133

---

Summary for Variable msgfifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18497048

1

T1

11622

T4

48180

T5

54956

auto[1]

91127414

1

T1

556337

T4

155684

T5

102255

---

Summary for Variable msgfifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

108718379

1

T1

567959

T4

202220

T5

157211

auto[1]

906083

1

T4

1644

T7

90

T8

133