Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99323213	1			T1	572634		T4	183765		T5	157832
all_pins[1]	99323213	1			T1	572634		T4	183765		T5	157832
all_pins[2]	99323213	1			T1	572634		T4	183765		T5	157832

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	297180085	1			T1	171439		T4	551060		T5	473012
values[0x1]	789554	1			T1	3503		T4	235		T5	484
transitions[0x0=>0x1]	787601	1			T1	3503		T4	235		T5	484
transitions[0x1=>0x0]	787626	1			T1	3503		T4	235		T5	484

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98815170	1			T1	569131		T4	183586		T5	157348
all_pins[0]	values[0x1]	508043	1			T1	3503		T4	179		T5	484
all_pins[0]	transitions[0x0=>0x1]	508026	1			T1	3503		T4	179		T5	484
all_pins[0]	transitions[0x1=>0x0]	5617	1			T4	56		T45	25		T46	32
all_pins[1]	values[0x0]	99317579	1			T1	572634		T4	183709		T5	157832
all_pins[1]	values[0x1]	5634	1			T4	56		T45	25		T46	32
all_pins[1]	transitions[0x0=>0x1]	5375	1			T4	56		T45	25		T46	32
all_pins[1]	transitions[0x1=>0x0]	275618	1			T7	3208		T48	649		T36	3523
all_pins[2]	values[0x0]	99047336	1			T1	572634		T4	183765		T5	157832
all_pins[2]	values[0x1]	275877	1			T7	3208		T48	649		T36	3523
all_pins[2]	transitions[0x0=>0x1]	274200	1			T7	3192		T48	649		T36	3501
all_pins[2]	transitions[0x1=>0x0]	506391	1			T1	3503		T4	179		T5	484