Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10851629 |
1 |
|
|
T1 |
27235 |
|
T4 |
18918 |
|
T5 |
3720 |
auto[1] |
10851629 |
1 |
|
|
T1 |
27235 |
|
T4 |
18918 |
|
T5 |
3720 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21463552 |
1 |
|
|
T1 |
52796 |
|
T4 |
37652 |
|
T5 |
7440 |
triple_byte_access |
79636 |
1 |
|
|
T1 |
558 |
|
T4 |
64 |
|
T13 |
558 |
halfword_access |
80328 |
1 |
|
|
T1 |
558 |
|
T4 |
50 |
|
T13 |
558 |
byte_access |
79742 |
1 |
|
|
T1 |
558 |
|
T4 |
70 |
|
T13 |
558 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10731776 |
1 |
|
|
T1 |
26398 |
|
T4 |
18826 |
|
T5 |
3720 |
auto[0] |
triple_byte_access |
39818 |
1 |
|
|
T1 |
279 |
|
T4 |
32 |
|
T13 |
279 |
auto[0] |
halfword_access |
40164 |
1 |
|
|
T1 |
279 |
|
T4 |
25 |
|
T13 |
279 |
auto[0] |
byte_access |
39871 |
1 |
|
|
T1 |
279 |
|
T4 |
35 |
|
T13 |
279 |
auto[1] |
word_access |
10731776 |
1 |
|
|
T1 |
26398 |
|
T4 |
18826 |
|
T5 |
3720 |
auto[1] |
triple_byte_access |
39818 |
1 |
|
|
T1 |
279 |
|
T4 |
32 |
|
T13 |
279 |
auto[1] |
halfword_access |
40164 |
1 |
|
|
T1 |
279 |
|
T4 |
25 |
|
T13 |
279 |
auto[1] |
byte_access |
39871 |
1 |
|
|
T1 |
279 |
|
T4 |
35 |
|
T13 |
279 |