Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.95 98.10 92.66 99.89 95.45 95.91 98.89 97.75


Total test records in report: 1243
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T1055 /workspace/coverage/default/6.kmac_test_vectors_sha3_256.2964045410 Mar 24 01:58:06 PM PDT 24 Mar 24 02:32:21 PM PDT 24 19596991755 ps
T1056 /workspace/coverage/default/40.kmac_test_vectors_sha3_256.4042481765 Mar 24 02:08:01 PM PDT 24 Mar 24 02:46:13 PM PDT 24 753355148743 ps
T1057 /workspace/coverage/default/48.kmac_app.1226277803 Mar 24 02:12:37 PM PDT 24 Mar 24 02:15:11 PM PDT 24 4805800383 ps
T1058 /workspace/coverage/default/11.kmac_test_vectors_kmac.3235058306 Mar 24 01:58:47 PM PDT 24 Mar 24 01:58:54 PM PDT 24 183563510 ps
T1059 /workspace/coverage/default/20.kmac_test_vectors_sha3_512.983285164 Mar 24 02:00:53 PM PDT 24 Mar 24 02:20:22 PM PDT 24 21195170496 ps
T1060 /workspace/coverage/default/30.kmac_test_vectors_shake_256.2213831212 Mar 24 02:04:21 PM PDT 24 Mar 24 03:15:19 PM PDT 24 78056789742 ps
T1061 /workspace/coverage/default/28.kmac_test_vectors_sha3_224.3491674115 Mar 24 02:03:25 PM PDT 24 Mar 24 02:38:59 PM PDT 24 97959596944 ps
T1062 /workspace/coverage/default/33.kmac_app.340207030 Mar 24 02:05:25 PM PDT 24 Mar 24 02:07:31 PM PDT 24 17762861845 ps
T1063 /workspace/coverage/default/26.kmac_smoke.2627724358 Mar 24 02:02:39 PM PDT 24 Mar 24 02:02:58 PM PDT 24 736783293 ps
T1064 /workspace/coverage/default/39.kmac_lc_escalation.3942600180 Mar 24 02:07:51 PM PDT 24 Mar 24 02:07:52 PM PDT 24 70196282 ps
T1065 /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.1287206591 Mar 24 02:01:35 PM PDT 24 Mar 24 02:01:42 PM PDT 24 889210706 ps
T1066 /workspace/coverage/default/31.kmac_lc_escalation.2701432174 Mar 24 02:04:50 PM PDT 24 Mar 24 02:04:54 PM PDT 24 71293589 ps
T1067 /workspace/coverage/default/36.kmac_test_vectors_sha3_256.4050711671 Mar 24 02:06:20 PM PDT 24 Mar 24 02:39:23 PM PDT 24 21628148439 ps
T1068 /workspace/coverage/default/38.kmac_test_vectors_sha3_512.4187348129 Mar 24 02:07:13 PM PDT 24 Mar 24 02:31:03 PM PDT 24 642198585806 ps
T1069 /workspace/coverage/default/7.kmac_sideload.2360717545 Mar 24 01:58:13 PM PDT 24 Mar 24 01:59:01 PM PDT 24 2057786493 ps
T1070 /workspace/coverage/default/45.kmac_test_vectors_shake_128.1606556604 Mar 24 02:10:57 PM PDT 24 Mar 24 03:37:19 PM PDT 24 389396990121 ps
T1071 /workspace/coverage/default/31.kmac_test_vectors_sha3_256.3727596042 Mar 24 02:04:40 PM PDT 24 Mar 24 02:34:21 PM PDT 24 189694396214 ps
T1072 /workspace/coverage/default/16.kmac_smoke.1676250982 Mar 24 01:59:49 PM PDT 24 Mar 24 02:00:52 PM PDT 24 40558641165 ps
T1073 /workspace/coverage/default/15.kmac_entropy_mode_error.2375491397 Mar 24 01:59:43 PM PDT 24 Mar 24 01:59:44 PM PDT 24 61340436 ps
T1074 /workspace/coverage/default/20.kmac_sideload.799534990 Mar 24 02:00:54 PM PDT 24 Mar 24 02:09:39 PM PDT 24 77996620767 ps
T1075 /workspace/coverage/default/34.kmac_error.54009422 Mar 24 02:05:43 PM PDT 24 Mar 24 02:13:48 PM PDT 24 169360900449 ps
T1076 /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.1023411582 Mar 24 02:05:40 PM PDT 24 Mar 24 02:05:46 PM PDT 24 722949564 ps
T1077 /workspace/coverage/default/14.kmac_alert_test.1673126370 Mar 24 01:59:35 PM PDT 24 Mar 24 01:59:36 PM PDT 24 162406051 ps
T1078 /workspace/coverage/default/45.kmac_app.4076550994 Mar 24 02:11:05 PM PDT 24 Mar 24 02:17:17 PM PDT 24 9967551402 ps
T1079 /workspace/coverage/default/4.kmac_test_vectors_sha3_224.2183473513 Mar 24 01:57:52 PM PDT 24 Mar 24 02:33:25 PM PDT 24 68931661238 ps
T1080 /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.2822237216 Mar 24 02:06:04 PM PDT 24 Mar 24 02:06:11 PM PDT 24 443291400 ps
T75 /workspace/coverage/default/17.kmac_lc_escalation.735107977 Mar 24 02:00:16 PM PDT 24 Mar 24 02:00:18 PM PDT 24 141460641 ps
T1081 /workspace/coverage/default/48.kmac_alert_test.223407035 Mar 24 02:12:47 PM PDT 24 Mar 24 02:12:48 PM PDT 24 17227947 ps
T1082 /workspace/coverage/default/36.kmac_test_vectors_sha3_512.168704283 Mar 24 02:06:26 PM PDT 24 Mar 24 02:26:20 PM PDT 24 11089605104 ps
T134 /workspace/coverage/cover_reg_top/10.kmac_csr_rw.2112928568 Mar 24 12:36:33 PM PDT 24 Mar 24 12:36:35 PM PDT 24 104109130 ps
T114 /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.1277215495 Mar 24 12:36:09 PM PDT 24 Mar 24 12:36:10 PM PDT 24 22912403 ps
T115 /workspace/coverage/cover_reg_top/32.kmac_intr_test.980349372 Mar 24 12:36:35 PM PDT 24 Mar 24 12:36:36 PM PDT 24 20532625 ps
T111 /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1141148475 Mar 24 12:36:41 PM PDT 24 Mar 24 12:36:48 PM PDT 24 863232920 ps
T86 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1619919571 Mar 24 12:36:11 PM PDT 24 Mar 24 12:36:12 PM PDT 24 594755340 ps
T116 /workspace/coverage/cover_reg_top/36.kmac_intr_test.3544472379 Mar 24 12:36:21 PM PDT 24 Mar 24 12:36:22 PM PDT 24 12509063 ps
T174 /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.643325047 Mar 24 12:36:23 PM PDT 24 Mar 24 12:36:25 PM PDT 24 64899666 ps
T1083 /workspace/coverage/cover_reg_top/14.kmac_tl_errors.3687664714 Mar 24 12:36:20 PM PDT 24 Mar 24 12:36:23 PM PDT 24 63326629 ps
T135 /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.223221340 Mar 24 12:36:34 PM PDT 24 Mar 24 12:36:46 PM PDT 24 487535301 ps
T156 /workspace/coverage/cover_reg_top/48.kmac_intr_test.3471975785 Mar 24 12:36:20 PM PDT 24 Mar 24 12:36:21 PM PDT 24 42231520 ps
T136 /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.4249268713 Mar 24 12:36:18 PM PDT 24 Mar 24 12:36:40 PM PDT 24 8478737626 ps
T157 /workspace/coverage/cover_reg_top/41.kmac_intr_test.2043943907 Mar 24 12:36:22 PM PDT 24 Mar 24 12:36:24 PM PDT 24 37225161 ps
T83 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.643363522 Mar 24 12:36:20 PM PDT 24 Mar 24 12:36:22 PM PDT 24 371658592 ps
T1084 /workspace/coverage/cover_reg_top/12.kmac_csr_rw.1280785531 Mar 24 12:36:30 PM PDT 24 Mar 24 12:36:31 PM PDT 24 17555886 ps
T112 /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.4249043521 Mar 24 12:36:20 PM PDT 24 Mar 24 12:36:30 PM PDT 24 926547254 ps
T125 /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2930226856 Mar 24 12:36:13 PM PDT 24 Mar 24 12:36:14 PM PDT 24 18451690 ps
T1085 /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.3920823944 Mar 24 12:36:18 PM PDT 24 Mar 24 12:36:38 PM PDT 24 1028814381 ps
T113 /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3908318789 Mar 24 12:36:27 PM PDT 24 Mar 24 12:36:34 PM PDT 24 455453841 ps
T84 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3728807013 Mar 24 12:36:45 PM PDT 24 Mar 24 12:36:46 PM PDT 24 36514409 ps
T158 /workspace/coverage/cover_reg_top/46.kmac_intr_test.659934531 Mar 24 12:36:33 PM PDT 24 Mar 24 12:36:34 PM PDT 24 15522941 ps
T159 /workspace/coverage/cover_reg_top/21.kmac_intr_test.2729571864 Mar 24 12:36:51 PM PDT 24 Mar 24 12:36:52 PM PDT 24 16826732 ps
T85 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3352692606 Mar 24 12:36:17 PM PDT 24 Mar 24 12:36:19 PM PDT 24 28708432 ps
T161 /workspace/coverage/cover_reg_top/33.kmac_intr_test.671685568 Mar 24 12:36:37 PM PDT 24 Mar 24 12:36:42 PM PDT 24 23376258 ps
T1086 /workspace/coverage/cover_reg_top/0.kmac_mem_walk.2999129091 Mar 24 12:36:24 PM PDT 24 Mar 24 12:36:25 PM PDT 24 26100294 ps
T87 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.85171601 Mar 24 12:36:02 PM PDT 24 Mar 24 12:36:04 PM PDT 24 232766725 ps
T96 /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3352968437 Mar 24 12:36:18 PM PDT 24 Mar 24 12:36:19 PM PDT 24 68101210 ps
T137 /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3166939602 Mar 24 12:36:28 PM PDT 24 Mar 24 12:36:32 PM PDT 24 244434998 ps
T160 /workspace/coverage/cover_reg_top/39.kmac_intr_test.510074686 Mar 24 12:36:36 PM PDT 24 Mar 24 12:36:37 PM PDT 24 32083170 ps
T1087 /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.937695005 Mar 24 12:36:21 PM PDT 24 Mar 24 12:36:26 PM PDT 24 79911429 ps
T1088 /workspace/coverage/cover_reg_top/1.kmac_intr_test.2474883398 Mar 24 12:36:15 PM PDT 24 Mar 24 12:36:16 PM PDT 24 64957428 ps
T1089 /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1476192272 Mar 24 12:36:19 PM PDT 24 Mar 24 12:36:21 PM PDT 24 28431337 ps
T1090 /workspace/coverage/cover_reg_top/43.kmac_intr_test.3502650398 Mar 24 12:36:27 PM PDT 24 Mar 24 12:36:30 PM PDT 24 39040246 ps
T138 /workspace/coverage/cover_reg_top/3.kmac_csr_rw.1957821551 Mar 24 12:36:21 PM PDT 24 Mar 24 12:36:23 PM PDT 24 44676612 ps
T166 /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1950782657 Mar 24 12:36:27 PM PDT 24 Mar 24 12:36:32 PM PDT 24 402172382 ps
T1091 /workspace/coverage/cover_reg_top/4.kmac_csr_rw.1492835214 Mar 24 12:36:09 PM PDT 24 Mar 24 12:36:10 PM PDT 24 22229734 ps
T162 /workspace/coverage/cover_reg_top/2.kmac_intr_test.2219249321 Mar 24 12:36:20 PM PDT 24 Mar 24 12:36:24 PM PDT 24 17771490 ps
T93 /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3050707420 Mar 24 12:36:34 PM PDT 24 Mar 24 12:36:36 PM PDT 24 126422897 ps
T1092 /workspace/coverage/cover_reg_top/0.kmac_tl_errors.2953929135 Mar 24 12:36:07 PM PDT 24 Mar 24 12:36:10 PM PDT 24 41788019 ps
T1093 /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1957776668 Mar 24 12:36:25 PM PDT 24 Mar 24 12:36:27 PM PDT 24 115214461 ps
T1094 /workspace/coverage/cover_reg_top/6.kmac_tl_errors.3775543344 Mar 24 12:36:09 PM PDT 24 Mar 24 12:36:12 PM PDT 24 214424631 ps
T152 /workspace/coverage/cover_reg_top/8.kmac_tl_errors.3342997440 Mar 24 12:36:24 PM PDT 24 Mar 24 12:36:28 PM PDT 24 152700665 ps
T167 /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.231502467 Mar 24 12:36:37 PM PDT 24 Mar 24 12:36:46 PM PDT 24 449237030 ps
T1095 /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2806573771 Mar 24 12:36:27 PM PDT 24 Mar 24 12:36:31 PM PDT 24 90539385 ps
T94 /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2661254037 Mar 24 12:36:10 PM PDT 24 Mar 24 12:36:12 PM PDT 24 95089413 ps
T154 /workspace/coverage/cover_reg_top/9.kmac_tl_errors.621063178 Mar 24 12:36:21 PM PDT 24 Mar 24 12:36:25 PM PDT 24 372319919 ps
T126 /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.117602243 Mar 24 12:36:22 PM PDT 24 Mar 24 12:36:24 PM PDT 24 231940878 ps
T89 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3915386803 Mar 24 12:36:32 PM PDT 24 Mar 24 12:36:36 PM PDT 24 738782842 ps
T1096 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3305501830 Mar 24 12:36:21 PM PDT 24 Mar 24 12:36:24 PM PDT 24 22357486 ps
T139 /workspace/coverage/cover_reg_top/6.kmac_csr_rw.587669318 Mar 24 12:36:21 PM PDT 24 Mar 24 12:36:24 PM PDT 24 23124807 ps
T1097 /workspace/coverage/cover_reg_top/3.kmac_mem_walk.2445234193 Mar 24 12:36:19 PM PDT 24 Mar 24 12:36:20 PM PDT 24 32527512 ps
T1098 /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.565018853 Mar 24 12:36:13 PM PDT 24 Mar 24 12:36:26 PM PDT 24 149188736 ps
T1099 /workspace/coverage/cover_reg_top/19.kmac_csr_rw.1795466772 Mar 24 12:36:34 PM PDT 24 Mar 24 12:36:36 PM PDT 24 308453570 ps
T150 /workspace/coverage/cover_reg_top/17.kmac_intr_test.225105319 Mar 24 12:36:16 PM PDT 24 Mar 24 12:36:19 PM PDT 24 51959481 ps
T1100 /workspace/coverage/cover_reg_top/16.kmac_csr_rw.193102742 Mar 24 12:36:42 PM PDT 24 Mar 24 12:36:44 PM PDT 24 22149392 ps
T1101 /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2965172096 Mar 24 12:36:46 PM PDT 24 Mar 24 12:36:48 PM PDT 24 116627566 ps
T1102 /workspace/coverage/cover_reg_top/30.kmac_intr_test.3987835994 Mar 24 12:36:47 PM PDT 24 Mar 24 12:36:48 PM PDT 24 15057666 ps
T1103 /workspace/coverage/cover_reg_top/11.kmac_csr_rw.3270813624 Mar 24 12:36:38 PM PDT 24 Mar 24 12:36:44 PM PDT 24 19000520 ps
T1104 /workspace/coverage/cover_reg_top/47.kmac_intr_test.1940437798 Mar 24 12:36:34 PM PDT 24 Mar 24 12:36:36 PM PDT 24 15333869 ps
T151 /workspace/coverage/cover_reg_top/0.kmac_csr_rw.4036611497 Mar 24 12:36:33 PM PDT 24 Mar 24 12:36:34 PM PDT 24 79244165 ps
T1105 /workspace/coverage/cover_reg_top/11.kmac_tl_errors.484528316 Mar 24 12:36:34 PM PDT 24 Mar 24 12:36:37 PM PDT 24 45595252 ps
T168 /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.2207827109 Mar 24 12:36:42 PM PDT 24 Mar 24 12:36:46 PM PDT 24 184591081 ps
T1106 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1796013723 Mar 24 12:36:33 PM PDT 24 Mar 24 12:36:35 PM PDT 24 376129122 ps
T1107 /workspace/coverage/cover_reg_top/23.kmac_intr_test.158226318 Mar 24 12:36:25 PM PDT 24 Mar 24 12:36:28 PM PDT 24 15554124 ps
T1108 /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1813548450 Mar 24 12:36:41 PM PDT 24 Mar 24 12:36:45 PM PDT 24 35204999 ps
T140 /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3661054375 Mar 24 12:36:33 PM PDT 24 Mar 24 12:36:35 PM PDT 24 174147462 ps
T1109 /workspace/coverage/cover_reg_top/35.kmac_intr_test.4247944411 Mar 24 12:36:22 PM PDT 24 Mar 24 12:36:24 PM PDT 24 11442696 ps
T153 /workspace/coverage/cover_reg_top/17.kmac_csr_rw.3124613550 Mar 24 12:36:24 PM PDT 24 Mar 24 12:36:26 PM PDT 24 33367876 ps
T1110 /workspace/coverage/cover_reg_top/5.kmac_tl_errors.345989630 Mar 24 12:36:29 PM PDT 24 Mar 24 12:36:32 PM PDT 24 100405392 ps
T1111 /workspace/coverage/cover_reg_top/44.kmac_intr_test.1343871522 Mar 24 12:36:45 PM PDT 24 Mar 24 12:36:46 PM PDT 24 12493263 ps
T1112 /workspace/coverage/cover_reg_top/26.kmac_intr_test.2067869596 Mar 24 12:36:47 PM PDT 24 Mar 24 12:36:48 PM PDT 24 49191573 ps
T91 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2478913248 Mar 24 12:36:27 PM PDT 24 Mar 24 12:36:28 PM PDT 24 73524309 ps
T172 /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.41637141 Mar 24 12:36:19 PM PDT 24 Mar 24 12:36:28 PM PDT 24 374123536 ps
T1113 /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2183151844 Mar 24 12:36:40 PM PDT 24 Mar 24 12:36:45 PM PDT 24 66215242 ps
T173 /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3875389047 Mar 24 12:36:34 PM PDT 24 Mar 24 12:36:37 PM PDT 24 189695813 ps
T1114 /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.366825742 Mar 24 12:36:41 PM PDT 24 Mar 24 12:36:45 PM PDT 24 27961038 ps
T1115 /workspace/coverage/cover_reg_top/42.kmac_intr_test.78622176 Mar 24 12:36:19 PM PDT 24 Mar 24 12:36:20 PM PDT 24 53095214 ps
T1116 /workspace/coverage/cover_reg_top/10.kmac_tl_errors.3305431629 Mar 24 12:36:34 PM PDT 24 Mar 24 12:36:37 PM PDT 24 33250281 ps
T92 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1560362912 Mar 24 12:36:35 PM PDT 24 Mar 24 12:36:37 PM PDT 24 58472561 ps
T1117 /workspace/coverage/cover_reg_top/13.kmac_intr_test.3295223768 Mar 24 12:36:09 PM PDT 24 Mar 24 12:36:10 PM PDT 24 30852324 ps
T88 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3539620742 Mar 24 12:36:31 PM PDT 24 Mar 24 12:36:34 PM PDT 24 424343746 ps
T1118 /workspace/coverage/cover_reg_top/27.kmac_intr_test.2342554255 Mar 24 12:36:41 PM PDT 24 Mar 24 12:36:44 PM PDT 24 29761944 ps
T1119 /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.864461382 Mar 24 12:36:45 PM PDT 24 Mar 24 12:36:48 PM PDT 24 81004076 ps
T1120 /workspace/coverage/cover_reg_top/31.kmac_intr_test.2929411517 Mar 24 12:36:25 PM PDT 24 Mar 24 12:36:26 PM PDT 24 21665881 ps
T90 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.187957351 Mar 24 12:36:25 PM PDT 24 Mar 24 12:36:26 PM PDT 24 96282974 ps
T1121 /workspace/coverage/cover_reg_top/7.kmac_intr_test.3682915648 Mar 24 12:36:21 PM PDT 24 Mar 24 12:36:23 PM PDT 24 32917868 ps
T1122 /workspace/coverage/cover_reg_top/15.kmac_tl_errors.58512370 Mar 24 12:36:31 PM PDT 24 Mar 24 12:36:33 PM PDT 24 294090758 ps
T1123 /workspace/coverage/cover_reg_top/38.kmac_intr_test.2927833675 Mar 24 12:36:44 PM PDT 24 Mar 24 12:36:45 PM PDT 24 73337677 ps
T169 /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1450966697 Mar 24 12:36:14 PM PDT 24 Mar 24 12:36:19 PM PDT 24 213033691 ps
T110 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3009701749 Mar 24 12:36:19 PM PDT 24 Mar 24 12:36:22 PM PDT 24 1240891438 ps
T1124 /workspace/coverage/cover_reg_top/7.kmac_csr_rw.1531380254 Mar 24 12:36:40 PM PDT 24 Mar 24 12:36:44 PM PDT 24 39138299 ps
T1125 /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3138407191 Mar 24 12:36:31 PM PDT 24 Mar 24 12:36:32 PM PDT 24 25695140 ps
T1126 /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.4246283438 Mar 24 12:36:40 PM PDT 24 Mar 24 12:36:50 PM PDT 24 23938148 ps
T1127 /workspace/coverage/cover_reg_top/6.kmac_intr_test.4007463435 Mar 24 12:36:41 PM PDT 24 Mar 24 12:36:44 PM PDT 24 43910392 ps
T1128 /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3938927682 Mar 24 12:36:18 PM PDT 24 Mar 24 12:36:21 PM PDT 24 137851594 ps
T127 /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.1278040561 Mar 24 12:36:09 PM PDT 24 Mar 24 12:36:10 PM PDT 24 16457656 ps
T1129 /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.1409898317 Mar 24 12:36:09 PM PDT 24 Mar 24 12:36:14 PM PDT 24 290673303 ps
T1130 /workspace/coverage/cover_reg_top/13.kmac_tl_errors.4194278595 Mar 24 12:36:35 PM PDT 24 Mar 24 12:36:37 PM PDT 24 26745105 ps
T1131 /workspace/coverage/cover_reg_top/2.kmac_mem_walk.24891758 Mar 24 12:36:18 PM PDT 24 Mar 24 12:36:19 PM PDT 24 32086069 ps
T1132 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1854863577 Mar 24 12:36:27 PM PDT 24 Mar 24 12:36:31 PM PDT 24 76934108 ps
T1133 /workspace/coverage/cover_reg_top/8.kmac_csr_rw.1792647095 Mar 24 12:36:41 PM PDT 24 Mar 24 12:36:44 PM PDT 24 26358089 ps
T1134 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.26365463 Mar 24 12:36:43 PM PDT 24 Mar 24 12:36:46 PM PDT 24 393947214 ps
T1135 /workspace/coverage/cover_reg_top/14.kmac_csr_rw.2326198931 Mar 24 12:36:38 PM PDT 24 Mar 24 12:36:44 PM PDT 24 59015364 ps
T1136 /workspace/coverage/cover_reg_top/4.kmac_intr_test.2978767213 Mar 24 12:36:10 PM PDT 24 Mar 24 12:36:11 PM PDT 24 27917531 ps
T1137 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3705659943 Mar 24 12:36:32 PM PDT 24 Mar 24 12:36:35 PM PDT 24 55915628 ps
T1138 /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.10390386 Mar 24 12:36:37 PM PDT 24 Mar 24 12:36:39 PM PDT 24 125947681 ps
T1139 /workspace/coverage/cover_reg_top/28.kmac_intr_test.2378135438 Mar 24 12:36:36 PM PDT 24 Mar 24 12:36:37 PM PDT 24 82096616 ps
T170 /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.185659504 Mar 24 12:36:04 PM PDT 24 Mar 24 12:36:08 PM PDT 24 218149672 ps
T1140 /workspace/coverage/cover_reg_top/1.kmac_csr_rw.621964379 Mar 24 12:36:18 PM PDT 24 Mar 24 12:36:19 PM PDT 24 101329322 ps
T1141 /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.905196629 Mar 24 12:36:22 PM PDT 24 Mar 24 12:36:25 PM PDT 24 48293156 ps
T1142 /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2528131443 Mar 24 12:36:30 PM PDT 24 Mar 24 12:36:33 PM PDT 24 70339842 ps
T1143 /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2344356126 Mar 24 12:36:20 PM PDT 24 Mar 24 12:36:22 PM PDT 24 46154196 ps
T1144 /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3350615830 Mar 24 12:36:55 PM PDT 24 Mar 24 12:36:57 PM PDT 24 35156281 ps
T1145 /workspace/coverage/cover_reg_top/11.kmac_intr_test.1426493001 Mar 24 12:36:32 PM PDT 24 Mar 24 12:36:34 PM PDT 24 14378470 ps
T95 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.736720750 Mar 24 12:36:27 PM PDT 24 Mar 24 12:36:32 PM PDT 24 96159308 ps
T1146 /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1715452759 Mar 24 12:36:15 PM PDT 24 Mar 24 12:36:18 PM PDT 24 552552600 ps
T1147 /workspace/coverage/cover_reg_top/40.kmac_intr_test.1035048997 Mar 24 12:36:39 PM PDT 24 Mar 24 12:36:44 PM PDT 24 38903666 ps
T1148 /workspace/coverage/cover_reg_top/1.kmac_mem_walk.3411931891 Mar 24 12:36:06 PM PDT 24 Mar 24 12:36:07 PM PDT 24 11459095 ps
T1149 /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.147654555 Mar 24 12:36:19 PM PDT 24 Mar 24 12:36:21 PM PDT 24 269035009 ps
T1150 /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2612466150 Mar 24 12:36:22 PM PDT 24 Mar 24 12:36:24 PM PDT 24 20887456 ps
T1151 /workspace/coverage/cover_reg_top/49.kmac_intr_test.2363129268 Mar 24 12:36:45 PM PDT 24 Mar 24 12:36:45 PM PDT 24 16679145 ps
T1152 /workspace/coverage/cover_reg_top/0.kmac_intr_test.919305497 Mar 24 12:36:16 PM PDT 24 Mar 24 12:36:17 PM PDT 24 14900482 ps
T1153 /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.3471967098 Mar 24 12:36:29 PM PDT 24 Mar 24 12:36:34 PM PDT 24 452892573 ps
T1154 /workspace/coverage/cover_reg_top/20.kmac_intr_test.1312448049 Mar 24 12:36:43 PM PDT 24 Mar 24 12:36:44 PM PDT 24 88797489 ps
T1155 /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.381564407 Mar 24 12:36:41 PM PDT 24 Mar 24 12:36:47 PM PDT 24 350399833 ps
T1156 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3417894808 Mar 24 12:36:26 PM PDT 24 Mar 24 12:36:31 PM PDT 24 151360511 ps
T1157 /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.4267182222 Mar 24 12:36:12 PM PDT 24 Mar 24 12:36:14 PM PDT 24 30556972 ps
T1158 /workspace/coverage/cover_reg_top/18.kmac_intr_test.3073453669 Mar 24 12:36:35 PM PDT 24 Mar 24 12:36:36 PM PDT 24 20568158 ps
T1159 /workspace/coverage/cover_reg_top/34.kmac_intr_test.1116248116 Mar 24 12:36:35 PM PDT 24 Mar 24 12:36:37 PM PDT 24 28316050 ps
T1160 /workspace/coverage/cover_reg_top/9.kmac_intr_test.1618105511 Mar 24 12:36:37 PM PDT 24 Mar 24 12:36:44 PM PDT 24 104006460 ps
T1161 /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3893193477 Mar 24 12:36:21 PM PDT 24 Mar 24 12:36:27 PM PDT 24 1018994060 ps
T1162 /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.3499037714 Mar 24 12:36:17 PM PDT 24 Mar 24 12:36:21 PM PDT 24 142620285 ps
T1163 /workspace/coverage/cover_reg_top/12.kmac_tl_errors.1700891998 Mar 24 12:36:32 PM PDT 24 Mar 24 12:36:34 PM PDT 24 374910060 ps
T1164 /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2793833044 Mar 24 12:36:28 PM PDT 24 Mar 24 12:36:32 PM PDT 24 800596948 ps
T1165 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2999523956 Mar 24 12:36:45 PM PDT 24 Mar 24 12:36:47 PM PDT 24 387474598 ps
T1166 /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.10517255 Mar 24 12:36:03 PM PDT 24 Mar 24 12:36:05 PM PDT 24 42349801 ps
T1167 /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.844366945 Mar 24 12:36:35 PM PDT 24 Mar 24 12:36:38 PM PDT 24 147650462 ps
T1168 /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2654543928 Mar 24 12:36:20 PM PDT 24 Mar 24 12:36:24 PM PDT 24 157307289 ps
T1169 /workspace/coverage/cover_reg_top/22.kmac_intr_test.3256181681 Mar 24 12:36:16 PM PDT 24 Mar 24 12:36:18 PM PDT 24 40296133 ps
T1170 /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2840990158 Mar 24 12:36:23 PM PDT 24 Mar 24 12:36:26 PM PDT 24 86938417 ps
T1171 /workspace/coverage/cover_reg_top/45.kmac_intr_test.2867061230 Mar 24 12:36:24 PM PDT 24 Mar 24 12:36:26 PM PDT 24 26905348 ps
T1172 /workspace/coverage/cover_reg_top/10.kmac_intr_test.586831903 Mar 24 12:36:36 PM PDT 24 Mar 24 12:36:37 PM PDT 24 18539072 ps
T1173 /workspace/coverage/cover_reg_top/5.kmac_csr_rw.152411981 Mar 24 12:36:40 PM PDT 24 Mar 24 12:36:44 PM PDT 24 103502526 ps
T1174 /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.690993207 Mar 24 12:36:44 PM PDT 24 Mar 24 12:36:45 PM PDT 24 52640617 ps
T1175 /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1534699049 Mar 24 12:36:34 PM PDT 24 Mar 24 12:36:37 PM PDT 24 28123190 ps
T1176 /workspace/coverage/cover_reg_top/17.kmac_tl_errors.4267194942 Mar 24 12:36:33 PM PDT 24 Mar 24 12:36:35 PM PDT 24 78557913 ps
T128 /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2755973068 Mar 24 12:36:21 PM PDT 24 Mar 24 12:36:26 PM PDT 24 68687080 ps
T1177 /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2224700009 Mar 24 12:36:27 PM PDT 24 Mar 24 12:36:32 PM PDT 24 687317131 ps
T1178 /workspace/coverage/cover_reg_top/14.kmac_intr_test.618805306 Mar 24 12:36:31 PM PDT 24 Mar 24 12:36:32 PM PDT 24 39335943 ps
T1179 /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1177222556 Mar 24 12:36:25 PM PDT 24 Mar 24 12:36:27 PM PDT 24 160658437 ps
T1180 /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3788481611 Mar 24 12:36:33 PM PDT 24 Mar 24 12:36:35 PM PDT 24 227932106 ps
T1181 /workspace/coverage/cover_reg_top/15.kmac_csr_rw.57361024 Mar 24 12:36:23 PM PDT 24 Mar 24 12:36:25 PM PDT 24 19714330 ps
T1182 /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2010568462 Mar 24 12:36:24 PM PDT 24 Mar 24 12:36:27 PM PDT 24 133778390 ps
T1183 /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.436316793 Mar 24 12:36:22 PM PDT 24 Mar 24 12:36:31 PM PDT 24 25783603 ps
T1184 /workspace/coverage/cover_reg_top/5.kmac_intr_test.3624228215 Mar 24 12:36:23 PM PDT 24 Mar 24 12:36:24 PM PDT 24 12389727 ps
T1185 /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1723705678 Mar 24 12:36:07 PM PDT 24 Mar 24 12:36:09 PM PDT 24 207848965 ps
T1186 /workspace/coverage/cover_reg_top/2.kmac_csr_rw.990508787 Mar 24 12:36:14 PM PDT 24 Mar 24 12:36:15 PM PDT 24 24024881 ps
T1187 /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.4261998129 Mar 24 12:36:10 PM PDT 24 Mar 24 12:36:12 PM PDT 24 18777559 ps
T1188 /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3905015994 Mar 24 12:36:12 PM PDT 24 Mar 24 12:36:14 PM PDT 24 241270426 ps
T1189 /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.409067190 Mar 24 12:36:41 PM PDT 24 Mar 24 12:36:46 PM PDT 24 340724370 ps
T1190 /workspace/coverage/cover_reg_top/16.kmac_tl_errors.134668795 Mar 24 12:36:42 PM PDT 24 Mar 24 12:36:50 PM PDT 24 228034369 ps
T1191 /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2331076953 Mar 24 12:36:18 PM PDT 24 Mar 24 12:36:43 PM PDT 24 3998279153 ps
T1192 /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1880845850 Mar 24 12:36:12 PM PDT 24 Mar 24 12:36:15 PM PDT 24 132441929 ps
T1193 /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3212755749 Mar 24 12:36:21 PM PDT 24 Mar 24 12:36:23 PM PDT 24 162199466 ps
T1194 /workspace/coverage/cover_reg_top/4.kmac_mem_walk.4212996527 Mar 24 12:36:29 PM PDT 24 Mar 24 12:36:31 PM PDT 24 23628686 ps
T1195 /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.1165826050 Mar 24 12:36:23 PM PDT 24 Mar 24 12:36:24 PM PDT 24 98844379 ps
T1196 /workspace/coverage/cover_reg_top/4.kmac_tl_errors.962718214 Mar 24 12:36:20 PM PDT 24 Mar 24 12:36:23 PM PDT 24 1774145877 ps
T1197 /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.3007835197 Mar 24 12:36:27 PM PDT 24 Mar 24 12:36:33 PM PDT 24 621199000 ps
T1198 /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2769736226 Mar 24 12:36:15 PM PDT 24 Mar 24 12:36:21 PM PDT 24 278912390 ps
T1199 /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.3537323661 Mar 24 12:36:34 PM PDT 24 Mar 24 12:36:38 PM PDT 24 793002995 ps
T1200 /workspace/coverage/cover_reg_top/8.kmac_intr_test.544541951 Mar 24 12:36:28 PM PDT 24 Mar 24 12:36:31 PM PDT 24 25268450 ps
T1201 /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1930606743 Mar 24 12:36:18 PM PDT 24 Mar 24 12:36:20 PM PDT 24 55947720 ps
T1202 /workspace/coverage/cover_reg_top/9.kmac_csr_rw.2244084346 Mar 24 12:36:15 PM PDT 24 Mar 24 12:36:17 PM PDT 24 22955627 ps
T1203 /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.2630144549 Mar 24 12:36:14 PM PDT 24 Mar 24 12:36:33 PM PDT 24 2537272605 ps
T1204 /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.687377967 Mar 24 12:36:35 PM PDT 24 Mar 24 12:36:38 PM PDT 24 56017396 ps
T1205 /workspace/coverage/cover_reg_top/13.kmac_csr_rw.572255399 Mar 24 12:36:17 PM PDT 24 Mar 24 12:36:19 PM PDT 24 37972595 ps
T1206 /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3174521396 Mar 24 12:36:10 PM PDT 24 Mar 24 12:36:13 PM PDT 24 544219325 ps
T1207 /workspace/coverage/cover_reg_top/16.kmac_intr_test.2322411765 Mar 24 12:36:30 PM PDT 24 Mar 24 12:36:32 PM PDT 24 10969009 ps
T1208 /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1746135855 Mar 24 12:36:21 PM PDT 24 Mar 24 12:36:23 PM PDT 24 51410826 ps
T1209 /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3295868027 Mar 24 12:36:41 PM PDT 24 Mar 24 12:36:46 PM PDT 24 81596757 ps
T1210 /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.4079356761 Mar 24 12:36:27 PM PDT 24 Mar 24 12:36:31 PM PDT 24 41891094 ps
T1211 /workspace/coverage/cover_reg_top/25.kmac_intr_test.2674687310 Mar 24 12:36:42 PM PDT 24 Mar 24 12:36:44 PM PDT 24 17291944 ps
T1212 /workspace/coverage/cover_reg_top/1.kmac_tl_errors.3654623005 Mar 24 12:36:42 PM PDT 24 Mar 24 12:36:46 PM PDT 24 129380547 ps
T1213 /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2006450485 Mar 24 12:36:27 PM PDT 24 Mar 24 12:36:31 PM PDT 24 145817926 ps
T1214 /workspace/coverage/cover_reg_top/3.kmac_intr_test.4187527507 Mar 24 12:36:44 PM PDT 24 Mar 24 12:36:45 PM PDT 24 44782841 ps
T1215 /workspace/coverage/cover_reg_top/12.kmac_intr_test.1034847273 Mar 24 12:36:33 PM PDT 24 Mar 24 12:36:34 PM PDT 24 44741127 ps
T1216 /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.219923915 Mar 24 12:36:32 PM PDT 24 Mar 24 12:36:35 PM PDT 24 142514747 ps
T1217 /workspace/coverage/cover_reg_top/18.kmac_tl_errors.4076465584 Mar 24 12:36:17 PM PDT 24 Mar 24 12:36:20 PM PDT 24 49047541 ps
T1218 /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1321348316 Mar 24 12:36:13 PM PDT 24 Mar 24 12:36:15 PM PDT 24 107762666 ps
T1219 /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2061870112 Mar 24 12:36:25 PM PDT 24 Mar 24 12:36:28 PM PDT 24 216093377 ps
T1220 /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.950384970 Mar 24 12:36:32 PM PDT 24 Mar 24 12:36:35 PM PDT 24 101691179 ps
T1221 /workspace/coverage/cover_reg_top/3.kmac_tl_errors.1378704805 Mar 24 12:36:08 PM PDT 24 Mar 24 12:36:10 PM PDT 24 117960009 ps
T1222 /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3867860698 Mar 24 12:36:09 PM PDT 24 Mar 24 12:36:11 PM PDT 24 90149778 ps
T1223 /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.2853738385 Mar 24 12:37:12 PM PDT 24 Mar 24 12:37:14 PM PDT 24 182260426 ps
T1224 /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.603207322 Mar 24 12:36:22 PM PDT 24 Mar 24 12:36:24 PM PDT 24 45542520 ps
T1225 /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3031900877 Mar 24 12:36:26 PM PDT 24 Mar 24 12:36:28 PM PDT 24 107331934 ps
T1226 /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2824186575 Mar 24 12:36:34 PM PDT 24 Mar 24 12:36:37 PM PDT 24 97813421 ps
T1227 /workspace/coverage/cover_reg_top/19.kmac_tl_errors.988748889 Mar 24 12:36:33 PM PDT 24 Mar 24 12:36:35 PM PDT 24 273268394 ps
T1228 /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3863690624 Mar 24 12:36:13 PM PDT 24 Mar 24 12:36:15 PM PDT 24 61804443 ps
T1229 /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3469168678 Mar 24 12:36:28 PM PDT 24 Mar 24 12:36:31 PM PDT 24 68838922 ps
T1230 /workspace/coverage/cover_reg_top/15.kmac_intr_test.4037940205 Mar 24 12:36:18 PM PDT 24 Mar 24 12:36:19 PM PDT 24 100148420 ps
T1231 /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.433711525 Mar 24 12:36:38 PM PDT 24 Mar 24 12:36:45 PM PDT 24 93010783 ps
T1232 /workspace/coverage/cover_reg_top/2.kmac_tl_errors.3457851386 Mar 24 12:36:23 PM PDT 24 Mar 24 12:36:27 PM PDT 24 102854157 ps
T1233 /workspace/coverage/cover_reg_top/37.kmac_intr_test.156954404 Mar 24 12:36:28 PM PDT 24 Mar 24 12:36:44 PM PDT 24 22676982 ps
T1234 /workspace/coverage/cover_reg_top/19.kmac_intr_test.2575630243 Mar 24 12:36:29 PM PDT 24 Mar 24 12:36:31 PM PDT 24 17695206 ps
T1235 /workspace/coverage/cover_reg_top/29.kmac_intr_test.224346128 Mar 24 12:36:52 PM PDT 24 Mar 24 12:36:54 PM PDT 24 98036354 ps
T1236 /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1887032410 Mar 24 12:36:07 PM PDT 24 Mar 24 12:36:09 PM PDT 24 33622665 ps
T1237 /workspace/coverage/cover_reg_top/18.kmac_csr_rw.2442938344 Mar 24 12:37:03 PM PDT 24 Mar 24 12:37:05 PM PDT 24 45610765 ps
T1238 /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3366104083 Mar 24 12:36:26 PM PDT 24 Mar 24 12:36:28 PM PDT 24 45376207 ps
T1239 /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3567257387 Mar 24 12:36:40 PM PDT 24 Mar 24 12:36:45 PM PDT 24 116422186 ps
T1240 /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.427880290 Mar 24 12:36:22 PM PDT 24 Mar 24 12:36:34 PM PDT 24 1498342991 ps
T1241 /workspace/coverage/cover_reg_top/24.kmac_intr_test.2966644567 Mar 24 12:36:41 PM PDT 24 Mar 24 12:36:44 PM PDT 24 47973885 ps
T1242 /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.1756723307 Mar 24 12:35:59 PM PDT 24 Mar 24 12:36:00 PM PDT 24 31809285 ps
T1243 /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.4083854112 Mar 24 12:36:46 PM PDT 24 Mar 24 12:36:47 PM PDT 24 379329845 ps
T129 /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3868412451 Mar 24 12:36:16 PM PDT 24 Mar 24 12:36:17 PM PDT 24 70350042 ps

Test location /workspace/coverage/default/35.kmac_stress_all.3787211674
Short name T7
Test name
Test status
Simulation time 691983802131 ps
CPU time 2232.61 seconds
Started Mar 24 02:06:15 PM PDT 24
Finished Mar 24 02:43:30 PM PDT 24
Peak memory 406368 kb
Host smart-39e091a1-1a41-4aa9-bd9d-1b067baf5537
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3787211674 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_stress_all.3787211674 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_stress_all_with_rand_reset.3875003775
Short name T36
Test name
Test status
Simulation time 26345550989 ps
CPU time 485.9 seconds
Started Mar 24 01:58:15 PM PDT 24
Finished Mar 24 02:06:21 PM PDT 24
Peak memory 271248 kb
Host smart-c2761e03-f8ad-4251-85e9-c2c39622b3ca
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3875003775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_rand_reset.3875003775 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_intg_err.4249043521
Short name T112
Test name
Test status
Simulation time 926547254 ps
CPU time 4.98 seconds
Started Mar 24 12:36:20 PM PDT 24
Finished Mar 24 12:36:30 PM PDT 24
Peak memory 216172 kb
Host smart-e169f043-7121-45ae-8057-12795b0b19ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249043521 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.4249
043521 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_sec_cm.3501920780
Short name T19
Test name
Test status
Simulation time 17263161061 ps
CPU time 62.57 seconds
Started Mar 24 01:57:34 PM PDT 24
Finished Mar 24 01:58:37 PM PDT 24
Peak memory 284676 kb
Host smart-46f54c8f-32cd-4fce-ac96-c62e26965e97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501920780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.3501920780 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/0.kmac_sec_cm/latest

Test location /workspace/coverage/default/22.kmac_lc_escalation.2414001302
Short name T376
Test name
Test status
Simulation time 141579968 ps
CPU time 1.48 seconds
Started Mar 24 02:01:44 PM PDT 24
Finished Mar 24 02:01:46 PM PDT 24
Peak memory 218832 kb
Host smart-2cea6ff3-57d0-44f8-8130-2bea6efbfc8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414001302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.2414001302 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/22.kmac_lc_escalation/latest

Test location /workspace/coverage/default/2.kmac_lc_escalation.3980430882
Short name T27
Test name
Test status
Simulation time 42698199 ps
CPU time 1.39 seconds
Started Mar 24 01:57:46 PM PDT 24
Finished Mar 24 01:57:47 PM PDT 24
Peak memory 218636 kb
Host smart-044da4d5-9268-4a07-aaea-762cea1697a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3980430882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.3980430882 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/2.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_error.113796439
Short name T58
Test name
Test status
Simulation time 62690011627 ps
CPU time 491.92 seconds
Started Mar 24 01:57:47 PM PDT 24
Finished Mar 24 02:05:59 PM PDT 24
Peak memory 267672 kb
Host smart-24a61b5c-fd68-4748-83ff-8dcd68eeec6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113796439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.113796439 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_error/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors.187957351
Short name T90
Test name
Test status
Simulation time 96282974 ps
CPU time 1.26 seconds
Started Mar 24 12:36:25 PM PDT 24
Finished Mar 24 12:36:26 PM PDT 24
Peak memory 217428 kb
Host smart-57f222df-0efc-40c2-977e-956a33aa23fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187957351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_e
rrors.187957351 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/16.kmac_key_error.1293559449
Short name T50
Test name
Test status
Simulation time 662152639 ps
CPU time 4.28 seconds
Started Mar 24 01:59:52 PM PDT 24
Finished Mar 24 01:59:57 PM PDT 24
Peak memory 218540 kb
Host smart-4b6aca06-ac09-4971-be8c-5d8255e2478d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293559449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.1293559449 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_key_error/latest

Test location /workspace/coverage/default/16.kmac_lc_escalation.2068781902
Short name T74
Test name
Test status
Simulation time 108615910 ps
CPU time 1.43 seconds
Started Mar 24 02:00:02 PM PDT 24
Finished Mar 24 02:00:03 PM PDT 24
Peak memory 219520 kb
Host smart-d9abc289-fc65-4173-b53f-e294dab8aa9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068781902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2068781902 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/16.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_entropy_ready_error.2231318044
Short name T522
Test name
Test status
Simulation time 3980381456 ps
CPU time 37.4 seconds
Started Mar 24 01:57:49 PM PDT 24
Finished Mar 24 01:58:27 PM PDT 24
Peak memory 226744 kb
Host smart-4a17ec07-5204-4c34-a4c2-5907d00d057f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231318044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.2231318044 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/11.kmac_edn_timeout_error.3969273281
Short name T306
Test name
Test status
Simulation time 30497482 ps
CPU time 1.19 seconds
Started Mar 24 01:58:49 PM PDT 24
Finished Mar 24 01:58:50 PM PDT 24
Peak memory 218632 kb
Host smart-418eac9a-eb04-4c37-b279-006f89a25ca3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3969273281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.3969273281 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_edn_timeout_error/latest

Test location /workspace/coverage/cover_reg_top/39.kmac_intr_test.510074686
Short name T160
Test name
Test status
Simulation time 32083170 ps
CPU time 0.8 seconds
Started Mar 24 12:36:36 PM PDT 24
Finished Mar 24 12:36:37 PM PDT 24
Peak memory 215904 kb
Host smart-3e1e1f16-0c0f-43b6-bb3f-b488714869eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510074686 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.kmac_intr_test.510074686 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/39.kmac_intr_test/latest

Test location /workspace/coverage/default/34.kmac_lc_escalation.2653983152
Short name T35
Test name
Test status
Simulation time 246937866 ps
CPU time 4.06 seconds
Started Mar 24 02:05:43 PM PDT 24
Finished Mar 24 02:05:48 PM PDT 24
Peak memory 226756 kb
Host smart-c955bfda-a68a-4a19-9213-6b9ca7feb9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653983152 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.2653983152 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/34.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_entropy_mode_error.1286147922
Short name T69
Test name
Test status
Simulation time 31135895 ps
CPU time 1.15 seconds
Started Mar 24 01:57:41 PM PDT 24
Finished Mar 24 01:57:42 PM PDT 24
Peak memory 222048 kb
Host smart-616571fc-d0fd-4501-b8fa-4dc5495dc516
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1286147922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.1286147922 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/44.kmac_lc_escalation.2483136180
Short name T931
Test name
Test status
Simulation time 139996876 ps
CPU time 1.39 seconds
Started Mar 24 02:10:47 PM PDT 24
Finished Mar 24 02:10:49 PM PDT 24
Peak memory 218608 kb
Host smart-ca76fb4a-e71c-453f-ad7c-c518b9b39632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483136180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.2483136180 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/44.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_app.2704086857
Short name T45
Test name
Test status
Simulation time 7623239449 ps
CPU time 303.15 seconds
Started Mar 24 02:01:11 PM PDT 24
Finished Mar 24 02:06:15 PM PDT 24
Peak memory 247772 kb
Host smart-13f39c0f-8f85-49cc-b2c6-fdc3a2353d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704086857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.2704086857 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_app/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_partial_access.3868412451
Short name T129
Test name
Test status
Simulation time 70350042 ps
CPU time 1.39 seconds
Started Mar 24 12:36:16 PM PDT 24
Finished Mar 24 12:36:17 PM PDT 24
Peak memory 216124 kb
Host smart-513dd5ae-c265-4f86-a1d4-9d0035204854
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868412451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partia
l_access.3868412451 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_partial_access/latest

Test location /workspace/coverage/default/10.kmac_lc_escalation.2240107363
Short name T76
Test name
Test status
Simulation time 205542576 ps
CPU time 1.36 seconds
Started Mar 24 01:58:37 PM PDT 24
Finished Mar 24 01:58:39 PM PDT 24
Peak memory 218640 kb
Host smart-220396c8-96d9-4541-965d-c7b2ee3c5abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240107363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.2240107363 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/10.kmac_lc_escalation/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors_with_csr_rw.643363522
Short name T83
Test name
Test status
Simulation time 371658592 ps
CPU time 2.62 seconds
Started Mar 24 12:36:20 PM PDT 24
Finished Mar 24 12:36:22 PM PDT 24
Peak memory 220120 kb
Host smart-1f8939f4-43d6-4983-98d0-00bcce664141
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643363522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac
_shadow_reg_errors_with_csr_rw.643363522 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_128.3950889342
Short name T13
Test name
Test status
Simulation time 62350021296 ps
CPU time 5065.14 seconds
Started Mar 24 02:09:14 PM PDT 24
Finished Mar 24 03:33:40 PM PDT 24
Peak memory 664124 kb
Host smart-8cbec3a5-728d-40d0-b492-df76bd2e7276
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3950889342 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_128.3950889342 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_alert_test.652401250
Short name T259
Test name
Test status
Simulation time 235542676 ps
CPU time 0.82 seconds
Started Mar 24 01:57:31 PM PDT 24
Finished Mar 24 01:57:32 PM PDT 24
Peak memory 218416 kb
Host smart-f184bdd9-ae6e-4863-a453-7d77310fc9c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652401250 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.652401250 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_alert_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_intg_err.231502467
Short name T167
Test name
Test status
Simulation time 449237030 ps
CPU time 4.92 seconds
Started Mar 24 12:36:37 PM PDT 24
Finished Mar 24 12:36:46 PM PDT 24
Peak memory 216148 kb
Host smart-d0319a95-3c54-422b-9e54-3662ebdc9084
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231502467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.23150
2467 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/2.kmac_entropy_refresh.1358387315
Short name T66
Test name
Test status
Simulation time 6388648687 ps
CPU time 110.56 seconds
Started Mar 24 01:57:45 PM PDT 24
Finished Mar 24 01:59:35 PM PDT 24
Peak memory 234952 kb
Host smart-9249011c-4d8b-4761-b14f-23817d00bf0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358387315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.1358387315 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/2.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_sec_cm.2858103696
Short name T81
Test name
Test status
Simulation time 3185232145 ps
CPU time 44.01 seconds
Started Mar 24 01:57:42 PM PDT 24
Finished Mar 24 01:58:26 PM PDT 24
Peak memory 257452 kb
Host smart-33d0eccf-bb02-4042-9e7f-dba80d4ac68b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858103696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.2858103696 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/1.kmac_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors_with_csr_rw.736720750
Short name T95
Test name
Test status
Simulation time 96159308 ps
CPU time 2.85 seconds
Started Mar 24 12:36:27 PM PDT 24
Finished Mar 24 12:36:32 PM PDT 24
Peak memory 220488 kb
Host smart-6188c760-d193-4f40-bba9-8d15a00d23c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736720750 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_
shadow_reg_errors_with_csr_rw.736720750 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/6.kmac_stress_all_with_rand_reset.3635867689
Short name T40
Test name
Test status
Simulation time 39979805803 ps
CPU time 1461.2 seconds
Started Mar 24 01:58:04 PM PDT 24
Finished Mar 24 02:22:25 PM PDT 24
Peak memory 341872 kb
Host smart-1825df53-9446-46c3-b6bd-84172a616824
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3635867689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_rand_reset.3635867689 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_intr_test.225105319
Short name T150
Test name
Test status
Simulation time 51959481 ps
CPU time 0.8 seconds
Started Mar 24 12:36:16 PM PDT 24
Finished Mar 24 12:36:19 PM PDT 24
Peak memory 215924 kb
Host smart-2e53f47f-eda9-44eb-a340-4d1f344e0096
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225105319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_intr_test.225105319 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_intr_test/latest

Test location /workspace/coverage/default/13.kmac_app.711991123
Short name T98
Test name
Test status
Simulation time 8815781806 ps
CPU time 354.86 seconds
Started Mar 24 01:59:13 PM PDT 24
Finished Mar 24 02:05:08 PM PDT 24
Peak memory 251420 kb
Host smart-0e73f3de-8ee3-4139-b160-0119d0e57ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711991123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.711991123 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_app/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_intg_err.2207827109
Short name T168
Test name
Test status
Simulation time 184591081 ps
CPU time 2.55 seconds
Started Mar 24 12:36:42 PM PDT 24
Finished Mar 24 12:36:46 PM PDT 24
Peak memory 216168 kb
Host smart-820f9b7e-590a-43d2-8f2b-9fc632dc8ffb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207827109 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.22078
27109 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_shadow_reg_errors.2061870112
Short name T1219
Test name
Test status
Simulation time 216093377 ps
CPU time 1.1 seconds
Started Mar 24 12:36:25 PM PDT 24
Finished Mar 24 12:36:28 PM PDT 24
Peak memory 216288 kb
Host smart-5e03c45a-fee0-4d6c-aed3-fa3c18d82b8d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061870112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_
errors.2061870112 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.kmac_stress_all.3598460472
Short name T238
Test name
Test status
Simulation time 8988229429 ps
CPU time 91.41 seconds
Started Mar 24 02:00:14 PM PDT 24
Finished Mar 24 02:01:45 PM PDT 24
Peak memory 232664 kb
Host smart-40a0175f-09bf-4f63-8d16-43fb99f684b8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3598460472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all.3598460472 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_burst_write.3818797417
Short name T132
Test name
Test status
Simulation time 14242725384 ps
CPU time 1423.7 seconds
Started Mar 24 01:59:35 PM PDT 24
Finished Mar 24 02:23:19 PM PDT 24
Peak memory 243204 kb
Host smart-5b61d243-3561-49f2-8518-8389ec861da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818797417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.3818797417 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_burst_write/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_aliasing.565018853
Short name T1098
Test name
Test status
Simulation time 149188736 ps
CPU time 8.07 seconds
Started Mar 24 12:36:13 PM PDT 24
Finished Mar 24 12:36:26 PM PDT 24
Peak memory 216136 kb
Host smart-4492869d-47bf-431a-87ce-82cc9a2cdc0d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565018853 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.56501885
3 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_bit_bash.2331076953
Short name T1191
Test name
Test status
Simulation time 3998279153 ps
CPU time 20.26 seconds
Started Mar 24 12:36:18 PM PDT 24
Finished Mar 24 12:36:43 PM PDT 24
Peak memory 216192 kb
Host smart-c589a1d7-a4a1-438b-848f-3822ae745a12
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331076953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.2331076
953 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_hw_reset.1723705678
Short name T1185
Test name
Test status
Simulation time 207848965 ps
CPU time 0.97 seconds
Started Mar 24 12:36:07 PM PDT 24
Finished Mar 24 12:36:09 PM PDT 24
Peak memory 215952 kb
Host smart-a6a0cc9c-ef8f-4f02-8bcd-d6d93754d1ce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723705678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1723705
678 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_mem_rw_with_rand_reset.2344356126
Short name T1143
Test name
Test status
Simulation time 46154196 ps
CPU time 1.66 seconds
Started Mar 24 12:36:20 PM PDT 24
Finished Mar 24 12:36:22 PM PDT 24
Peak memory 217300 kb
Host smart-70ca9019-ec50-4ccf-840d-b9cb3d2e485d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344356126 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.2344356126 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_csr_rw.4036611497
Short name T151
Test name
Test status
Simulation time 79244165 ps
CPU time 1 seconds
Started Mar 24 12:36:33 PM PDT 24
Finished Mar 24 12:36:34 PM PDT 24
Peak memory 215928 kb
Host smart-48ea20dc-a21a-4f11-b481-70bd78f0921e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036611497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.4036611497 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_intr_test.919305497
Short name T1152
Test name
Test status
Simulation time 14900482 ps
CPU time 0.88 seconds
Started Mar 24 12:36:16 PM PDT 24
Finished Mar 24 12:36:17 PM PDT 24
Peak memory 215900 kb
Host smart-2010e4aa-ec85-415f-9f6f-af99c04cd96b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919305497 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.919305497 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/0.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_mem_walk.2999129091
Short name T1086
Test name
Test status
Simulation time 26100294 ps
CPU time 0.71 seconds
Started Mar 24 12:36:24 PM PDT 24
Finished Mar 24 12:36:25 PM PDT 24
Peak memory 215884 kb
Host smart-a7d32cc4-7591-475b-bf95-0ed9b747672f
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999129091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.2999129091
+enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_same_csr_outstanding.10517255
Short name T1166
Test name
Test status
Simulation time 42349801 ps
CPU time 2.16 seconds
Started Mar 24 12:36:03 PM PDT 24
Finished Mar 24 12:36:05 PM PDT 24
Peak memory 216180 kb
Host smart-3c111bb4-77d0-4534-8c85-53c1e3ce4828
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10517255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_o
utstanding.10517255 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_errors.2953929135
Short name T1092
Test name
Test status
Simulation time 41788019 ps
CPU time 2.57 seconds
Started Mar 24 12:36:07 PM PDT 24
Finished Mar 24 12:36:10 PM PDT 24
Peak memory 216156 kb
Host smart-2f55e124-f5c1-43cd-9150-97227591c6bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953929135 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.2953929135 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.kmac_tl_intg_err.185659504
Short name T170
Test name
Test status
Simulation time 218149672 ps
CPU time 4.58 seconds
Started Mar 24 12:36:04 PM PDT 24
Finished Mar 24 12:36:08 PM PDT 24
Peak memory 216156 kb
Host smart-b4affe9c-8daa-46b0-afe8-74e9693609bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185659504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.185659
504 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_aliasing.2769736226
Short name T1198
Test name
Test status
Simulation time 278912390 ps
CPU time 5.39 seconds
Started Mar 24 12:36:15 PM PDT 24
Finished Mar 24 12:36:21 PM PDT 24
Peak memory 216216 kb
Host smart-f62192be-1b8c-45b5-a429-23d0d223db1f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769736226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_aliasing.2769736
226 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_bit_bash.3920823944
Short name T1085
Test name
Test status
Simulation time 1028814381 ps
CPU time 19.66 seconds
Started Mar 24 12:36:18 PM PDT 24
Finished Mar 24 12:36:38 PM PDT 24
Peak memory 216104 kb
Host smart-b16229b4-eca1-451b-a464-d816363c9104
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920823944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_bit_bash.3920823
944 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_hw_reset.1277215495
Short name T114
Test name
Test status
Simulation time 22912403 ps
CPU time 1 seconds
Started Mar 24 12:36:09 PM PDT 24
Finished Mar 24 12:36:10 PM PDT 24
Peak memory 215936 kb
Host smart-f66d2b1b-424e-4ee5-943f-63ebe3c8e6af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277215495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_hw_reset.1277215
495 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_mem_rw_with_rand_reset.1887032410
Short name T1236
Test name
Test status
Simulation time 33622665 ps
CPU time 1.71 seconds
Started Mar 24 12:36:07 PM PDT 24
Finished Mar 24 12:36:09 PM PDT 24
Peak memory 220540 kb
Host smart-8309d603-84d5-4df6-97cf-33c1fef5c367
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887032410 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.1887032410 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_csr_rw.621964379
Short name T1140
Test name
Test status
Simulation time 101329322 ps
CPU time 1.29 seconds
Started Mar 24 12:36:18 PM PDT 24
Finished Mar 24 12:36:19 PM PDT 24
Peak memory 216072 kb
Host smart-3ae82fb4-71a3-4b31-80c2-fe76a7f96391
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621964379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.621964379 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/1.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_intr_test.2474883398
Short name T1088
Test name
Test status
Simulation time 64957428 ps
CPU time 0.76 seconds
Started Mar 24 12:36:15 PM PDT 24
Finished Mar 24 12:36:16 PM PDT 24
Peak memory 215944 kb
Host smart-9933ec2b-2537-42ad-877a-87ae04ca77e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474883398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.2474883398 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_partial_access.1278040561
Short name T127
Test name
Test status
Simulation time 16457656 ps
CPU time 1.11 seconds
Started Mar 24 12:36:09 PM PDT 24
Finished Mar 24 12:36:10 PM PDT 24
Peak memory 216124 kb
Host smart-12da6e74-3b75-4195-81d2-46d20fb5ed40
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278040561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_partia
l_access.1278040561 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_mem_walk.3411931891
Short name T1148
Test name
Test status
Simulation time 11459095 ps
CPU time 0.73 seconds
Started Mar 24 12:36:06 PM PDT 24
Finished Mar 24 12:36:07 PM PDT 24
Peak memory 215888 kb
Host smart-3bd922fb-de6a-4daa-960b-ea58c5141705
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411931891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_mem_walk.3411931891
+enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_same_csr_outstanding.2224700009
Short name T1177
Test name
Test status
Simulation time 687317131 ps
CPU time 2.48 seconds
Started Mar 24 12:36:27 PM PDT 24
Finished Mar 24 12:36:32 PM PDT 24
Peak memory 216096 kb
Host smart-475c8b33-0a03-4d72-9d97-28d26994b3f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224700009 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr
_outstanding.2224700009 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors.4079356761
Short name T1210
Test name
Test status
Simulation time 41891094 ps
CPU time 1.37 seconds
Started Mar 24 12:36:27 PM PDT 24
Finished Mar 24 12:36:31 PM PDT 24
Peak memory 217424 kb
Host smart-25f49fe2-2b66-4856-9e9b-c9f9e39eff62
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079356761 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_
errors.4079356761 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_shadow_reg_errors_with_csr_rw.3009701749
Short name T110
Test name
Test status
Simulation time 1240891438 ps
CPU time 3.26 seconds
Started Mar 24 12:36:19 PM PDT 24
Finished Mar 24 12:36:22 PM PDT 24
Peak memory 219012 kb
Host smart-6a3b5f55-a284-4caa-9b60-183835439d58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009701749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac
_shadow_reg_errors_with_csr_rw.3009701749 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_errors.3654623005
Short name T1212
Test name
Test status
Simulation time 129380547 ps
CPU time 3.15 seconds
Started Mar 24 12:36:42 PM PDT 24
Finished Mar 24 12:36:46 PM PDT 24
Peak memory 216256 kb
Host smart-97691dd9-637f-4fc3-8036-e60f59c285ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654623005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3654623005 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.kmac_tl_intg_err.3537323661
Short name T1199
Test name
Test status
Simulation time 793002995 ps
CPU time 2.77 seconds
Started Mar 24 12:36:34 PM PDT 24
Finished Mar 24 12:36:38 PM PDT 24
Peak memory 216184 kb
Host smart-a856d1ac-5ca2-4df3-b6c7-115f0fd17dde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537323661 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.35373
23661 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_mem_rw_with_rand_reset.1534699049
Short name T1175
Test name
Test status
Simulation time 28123190 ps
CPU time 1.77 seconds
Started Mar 24 12:36:34 PM PDT 24
Finished Mar 24 12:36:37 PM PDT 24
Peak memory 220304 kb
Host smart-a9719120-9217-4b96-9d01-74be4c46b364
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534699049 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 10.kmac_csr_mem_rw_with_rand_reset.1534699049 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_csr_rw.2112928568
Short name T134
Test name
Test status
Simulation time 104109130 ps
CPU time 1.27 seconds
Started Mar 24 12:36:33 PM PDT 24
Finished Mar 24 12:36:35 PM PDT 24
Peak memory 216136 kb
Host smart-30f12430-031d-4134-aba4-d68edbeb6500
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112928568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_csr_rw.2112928568 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_intr_test.586831903
Short name T1172
Test name
Test status
Simulation time 18539072 ps
CPU time 0.8 seconds
Started Mar 24 12:36:36 PM PDT 24
Finished Mar 24 12:36:37 PM PDT 24
Peak memory 215872 kb
Host smart-b7d20d49-88ae-46c0-bfe5-a5581d15ab05
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586831903 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_intr_test.586831903 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/10.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_same_csr_outstanding.219923915
Short name T1216
Test name
Test status
Simulation time 142514747 ps
CPU time 2.17 seconds
Started Mar 24 12:36:32 PM PDT 24
Finished Mar 24 12:36:35 PM PDT 24
Peak memory 216120 kb
Host smart-45cc83e6-bd2e-401f-ba69-1a9322b374cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219923915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_same_csr
_outstanding.219923915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors.3728807013
Short name T84
Test name
Test status
Simulation time 36514409 ps
CPU time 1.02 seconds
Started Mar 24 12:36:45 PM PDT 24
Finished Mar 24 12:36:46 PM PDT 24
Peak memory 216244 kb
Host smart-1da272ec-b022-4644-b9a5-2dffa969405c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728807013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg
_errors.3728807013 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_shadow_reg_errors_with_csr_rw.2654543928
Short name T1168
Test name
Test status
Simulation time 157307289 ps
CPU time 3.08 seconds
Started Mar 24 12:36:20 PM PDT 24
Finished Mar 24 12:36:24 PM PDT 24
Peak memory 219008 kb
Host smart-4ad3e4e0-74be-4996-86e9-7733630e7ef1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654543928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kma
c_shadow_reg_errors_with_csr_rw.2654543928 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_errors.3305431629
Short name T1116
Test name
Test status
Simulation time 33250281 ps
CPU time 1.99 seconds
Started Mar 24 12:36:34 PM PDT 24
Finished Mar 24 12:36:37 PM PDT 24
Peak memory 216188 kb
Host smart-7e3c0b4e-40f4-4eb6-b487-9c28b4fc1c55
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305431629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.3305431629 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.kmac_tl_intg_err.381564407
Short name T1155
Test name
Test status
Simulation time 350399833 ps
CPU time 4.07 seconds
Started Mar 24 12:36:41 PM PDT 24
Finished Mar 24 12:36:47 PM PDT 24
Peak memory 216132 kb
Host smart-76c8b2c6-05ed-431a-a4bb-888dffa5ee44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381564407 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.38156
4407 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_mem_rw_with_rand_reset.2612466150
Short name T1150
Test name
Test status
Simulation time 20887456 ps
CPU time 1.39 seconds
Started Mar 24 12:36:22 PM PDT 24
Finished Mar 24 12:36:24 PM PDT 24
Peak memory 217532 kb
Host smart-64937c2d-3abd-4d92-a345-dd69d4b7ce92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612466150 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.kmac_csr_mem_rw_with_rand_reset.2612466150 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_csr_rw.3270813624
Short name T1103
Test name
Test status
Simulation time 19000520 ps
CPU time 1.09 seconds
Started Mar 24 12:36:38 PM PDT 24
Finished Mar 24 12:36:44 PM PDT 24
Peak memory 216176 kb
Host smart-dbd1d636-df5a-4de0-936d-ac01e0e0d2eb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270813624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_csr_rw.3270813624 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_intr_test.1426493001
Short name T1145
Test name
Test status
Simulation time 14378470 ps
CPU time 0.83 seconds
Started Mar 24 12:36:32 PM PDT 24
Finished Mar 24 12:36:34 PM PDT 24
Peak memory 215892 kb
Host smart-100e1895-b433-47e0-9bea-e338ebbf0344
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426493001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_intr_test.1426493001 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_same_csr_outstanding.147654555
Short name T1149
Test name
Test status
Simulation time 269035009 ps
CPU time 1.85 seconds
Started Mar 24 12:36:19 PM PDT 24
Finished Mar 24 12:36:21 PM PDT 24
Peak memory 216148 kb
Host smart-e0580351-e57e-48df-86f7-6c401bde4a7c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=147654555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_same_csr
_outstanding.147654555 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors.2478913248
Short name T91
Test name
Test status
Simulation time 73524309 ps
CPU time 1.06 seconds
Started Mar 24 12:36:27 PM PDT 24
Finished Mar 24 12:36:28 PM PDT 24
Peak memory 216452 kb
Host smart-525cca35-8aac-4171-8c8b-9c3730230908
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478913248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg
_errors.2478913248 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_shadow_reg_errors_with_csr_rw.1177222556
Short name T1179
Test name
Test status
Simulation time 160658437 ps
CPU time 2.35 seconds
Started Mar 24 12:36:25 PM PDT 24
Finished Mar 24 12:36:27 PM PDT 24
Peak memory 219616 kb
Host smart-690e7cdb-4040-4c0a-9808-83ce19d2cd81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177222556 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kma
c_shadow_reg_errors_with_csr_rw.1177222556 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_errors.484528316
Short name T1105
Test name
Test status
Simulation time 45595252 ps
CPU time 1.51 seconds
Started Mar 24 12:36:34 PM PDT 24
Finished Mar 24 12:36:37 PM PDT 24
Peak memory 216208 kb
Host smart-30c55eee-b64c-4530-84ae-c192ca6ec7a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484528316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.484528316 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.kmac_tl_intg_err.3007835197
Short name T1197
Test name
Test status
Simulation time 621199000 ps
CPU time 3.09 seconds
Started Mar 24 12:36:27 PM PDT 24
Finished Mar 24 12:36:33 PM PDT 24
Peak memory 216480 kb
Host smart-146057c7-9723-4bc8-b28c-45dcf542b47c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007835197 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.3007
835197 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_mem_rw_with_rand_reset.2840990158
Short name T1170
Test name
Test status
Simulation time 86938417 ps
CPU time 1.56 seconds
Started Mar 24 12:36:23 PM PDT 24
Finished Mar 24 12:36:26 PM PDT 24
Peak memory 219104 kb
Host smart-7b4d18c9-09a0-458e-abbc-45b291c52def
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840990158 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 12.kmac_csr_mem_rw_with_rand_reset.2840990158 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_csr_rw.1280785531
Short name T1084
Test name
Test status
Simulation time 17555886 ps
CPU time 1.15 seconds
Started Mar 24 12:36:30 PM PDT 24
Finished Mar 24 12:36:31 PM PDT 24
Peak memory 216152 kb
Host smart-fd0b0257-0e32-4e78-a502-fe11b872eb48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280785531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_csr_rw.1280785531 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_intr_test.1034847273
Short name T1215
Test name
Test status
Simulation time 44741127 ps
CPU time 0.76 seconds
Started Mar 24 12:36:33 PM PDT 24
Finished Mar 24 12:36:34 PM PDT 24
Peak memory 215848 kb
Host smart-3341a8de-b4f2-431e-bb68-3ac8d098c38a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034847273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_intr_test.1034847273 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_same_csr_outstanding.3863690624
Short name T1228
Test name
Test status
Simulation time 61804443 ps
CPU time 1.64 seconds
Started Mar 24 12:36:13 PM PDT 24
Finished Mar 24 12:36:15 PM PDT 24
Peak memory 216512 kb
Host smart-6781793b-c7c0-428d-9fb3-cc668153a72d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863690624 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_same_cs
r_outstanding.3863690624 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_shadow_reg_errors_with_csr_rw.1880845850
Short name T1192
Test name
Test status
Simulation time 132441929 ps
CPU time 3.02 seconds
Started Mar 24 12:36:12 PM PDT 24
Finished Mar 24 12:36:15 PM PDT 24
Peak memory 218976 kb
Host smart-e0a9cc32-fe56-4a71-a7f0-b0eab6ea7615
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880845850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kma
c_shadow_reg_errors_with_csr_rw.1880845850 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_errors.1700891998
Short name T1163
Test name
Test status
Simulation time 374910060 ps
CPU time 2.07 seconds
Started Mar 24 12:36:32 PM PDT 24
Finished Mar 24 12:36:34 PM PDT 24
Peak memory 216540 kb
Host smart-517d150b-d1d1-4005-b763-f2f8af82d49a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700891998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.1700891998 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.kmac_tl_intg_err.1715452759
Short name T1146
Test name
Test status
Simulation time 552552600 ps
CPU time 2.95 seconds
Started Mar 24 12:36:15 PM PDT 24
Finished Mar 24 12:36:18 PM PDT 24
Peak memory 216132 kb
Host smart-c9c2d1bf-ba49-42b8-ab85-d99b475653b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715452759 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.1715
452759 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_mem_rw_with_rand_reset.2006450485
Short name T1213
Test name
Test status
Simulation time 145817926 ps
CPU time 1.54 seconds
Started Mar 24 12:36:27 PM PDT 24
Finished Mar 24 12:36:31 PM PDT 24
Peak memory 219596 kb
Host smart-f8bae925-7bb4-48d0-990d-5f1808ebaa8f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006450485 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 13.kmac_csr_mem_rw_with_rand_reset.2006450485 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_csr_rw.572255399
Short name T1205
Test name
Test status
Simulation time 37972595 ps
CPU time 0.95 seconds
Started Mar 24 12:36:17 PM PDT 24
Finished Mar 24 12:36:19 PM PDT 24
Peak memory 215960 kb
Host smart-2e75ac75-6a0b-49f2-94cb-72a5af70b907
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572255399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_csr_rw.572255399 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/13.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_intr_test.3295223768
Short name T1117
Test name
Test status
Simulation time 30852324 ps
CPU time 0.81 seconds
Started Mar 24 12:36:09 PM PDT 24
Finished Mar 24 12:36:10 PM PDT 24
Peak memory 215920 kb
Host smart-ba3aa619-aa74-4c3a-a6ed-83bec27442ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295223768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_intr_test.3295223768 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_same_csr_outstanding.433711525
Short name T1231
Test name
Test status
Simulation time 93010783 ps
CPU time 1.48 seconds
Started Mar 24 12:36:38 PM PDT 24
Finished Mar 24 12:36:45 PM PDT 24
Peak memory 216116 kb
Host smart-5ec3ffe8-e0ae-4579-ab69-471640ab890d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433711525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_same_csr
_outstanding.433711525 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors.3305501830
Short name T1096
Test name
Test status
Simulation time 22357486 ps
CPU time 1.1 seconds
Started Mar 24 12:36:21 PM PDT 24
Finished Mar 24 12:36:24 PM PDT 24
Peak memory 216536 kb
Host smart-26f217f9-55e1-400d-b3bb-315fb9403dd3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305501830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg
_errors.3305501830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_shadow_reg_errors_with_csr_rw.4267182222
Short name T1157
Test name
Test status
Simulation time 30556972 ps
CPU time 1.71 seconds
Started Mar 24 12:36:12 PM PDT 24
Finished Mar 24 12:36:14 PM PDT 24
Peak memory 216460 kb
Host smart-df6f78f9-b748-40a6-bd32-e9f3d3541a08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267182222 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kma
c_shadow_reg_errors_with_csr_rw.4267182222 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_errors.4194278595
Short name T1130
Test name
Test status
Simulation time 26745105 ps
CPU time 1.73 seconds
Started Mar 24 12:36:35 PM PDT 24
Finished Mar 24 12:36:37 PM PDT 24
Peak memory 216176 kb
Host smart-28f8a888-a8c5-4300-b928-22ae0f49cce0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194278595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.4194278595 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.kmac_tl_intg_err.3875389047
Short name T173
Test name
Test status
Simulation time 189695813 ps
CPU time 2.45 seconds
Started Mar 24 12:36:34 PM PDT 24
Finished Mar 24 12:36:37 PM PDT 24
Peak memory 216140 kb
Host smart-df720c1c-243f-430c-95ae-c6b5308fca5f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875389047 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3875
389047 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_mem_rw_with_rand_reset.1813548450
Short name T1108
Test name
Test status
Simulation time 35204999 ps
CPU time 1.97 seconds
Started Mar 24 12:36:41 PM PDT 24
Finished Mar 24 12:36:45 PM PDT 24
Peak memory 220936 kb
Host smart-2b8832ef-dabe-43c7-a9b4-6e7849bb725a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813548450 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 14.kmac_csr_mem_rw_with_rand_reset.1813548450 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_csr_rw.2326198931
Short name T1135
Test name
Test status
Simulation time 59015364 ps
CPU time 1.11 seconds
Started Mar 24 12:36:38 PM PDT 24
Finished Mar 24 12:36:44 PM PDT 24
Peak memory 216504 kb
Host smart-5af1303f-2d17-4692-a3f1-e940364cd291
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326198931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_csr_rw.2326198931 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_intr_test.618805306
Short name T1178
Test name
Test status
Simulation time 39335943 ps
CPU time 0.78 seconds
Started Mar 24 12:36:31 PM PDT 24
Finished Mar 24 12:36:32 PM PDT 24
Peak memory 215908 kb
Host smart-e72a4398-c41e-47a3-9dc1-c580c7eb36b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618805306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_intr_test.618805306 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/14.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_same_csr_outstanding.3138407191
Short name T1125
Test name
Test status
Simulation time 25695140 ps
CPU time 1.43 seconds
Started Mar 24 12:36:31 PM PDT 24
Finished Mar 24 12:36:32 PM PDT 24
Peak memory 216128 kb
Host smart-12607f9e-ce6f-42f2-8249-d4971560aa70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138407191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_same_cs
r_outstanding.3138407191 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_shadow_reg_errors.3050707420
Short name T93
Test name
Test status
Simulation time 126422897 ps
CPU time 1.24 seconds
Started Mar 24 12:36:34 PM PDT 24
Finished Mar 24 12:36:36 PM PDT 24
Peak memory 217440 kb
Host smart-ae81afa9-8196-4f63-a568-adecb41aee0e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050707420 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg
_errors.3050707420 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_errors.3687664714
Short name T1083
Test name
Test status
Simulation time 63326629 ps
CPU time 1.47 seconds
Started Mar 24 12:36:20 PM PDT 24
Finished Mar 24 12:36:23 PM PDT 24
Peak memory 216176 kb
Host smart-836cc12c-5291-4303-b3b0-e7d42768b8b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687664714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.3687664714 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.kmac_tl_intg_err.3908318789
Short name T113
Test name
Test status
Simulation time 455453841 ps
CPU time 4.77 seconds
Started Mar 24 12:36:27 PM PDT 24
Finished Mar 24 12:36:34 PM PDT 24
Peak memory 216508 kb
Host smart-14ccaa1b-9082-4034-b177-8000b038a69c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908318789 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.3908
318789 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_mem_rw_with_rand_reset.409067190
Short name T1189
Test name
Test status
Simulation time 340724370 ps
CPU time 2.54 seconds
Started Mar 24 12:36:41 PM PDT 24
Finished Mar 24 12:36:46 PM PDT 24
Peak memory 221116 kb
Host smart-424e93cb-bb76-4d4a-8029-5c5011e476f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409067190 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 15.kmac_csr_mem_rw_with_rand_reset.409067190 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_csr_rw.57361024
Short name T1181
Test name
Test status
Simulation time 19714330 ps
CPU time 1.12 seconds
Started Mar 24 12:36:23 PM PDT 24
Finished Mar 24 12:36:25 PM PDT 24
Peak memory 216148 kb
Host smart-e00f4402-586a-40bf-b86a-30a45d7e2b61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57361024 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_csr_rw.57361024 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/15.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_intr_test.4037940205
Short name T1230
Test name
Test status
Simulation time 100148420 ps
CPU time 0.81 seconds
Started Mar 24 12:36:18 PM PDT 24
Finished Mar 24 12:36:19 PM PDT 24
Peak memory 215920 kb
Host smart-460c2680-4167-4865-8240-69f41ee85120
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037940205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_intr_test.4037940205 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_same_csr_outstanding.4246283438
Short name T1126
Test name
Test status
Simulation time 23938148 ps
CPU time 1.45 seconds
Started Mar 24 12:36:40 PM PDT 24
Finished Mar 24 12:36:50 PM PDT 24
Peak memory 216104 kb
Host smart-aac49f30-c415-42f8-b5c9-eb4cf21ab8f1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246283438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_same_cs
r_outstanding.4246283438 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors.3352692606
Short name T85
Test name
Test status
Simulation time 28708432 ps
CPU time 0.97 seconds
Started Mar 24 12:36:17 PM PDT 24
Finished Mar 24 12:36:19 PM PDT 24
Peak memory 215980 kb
Host smart-540ea51b-3e72-4ef2-ac6e-fb95ae7cc846
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352692606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg
_errors.3352692606 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_shadow_reg_errors_with_csr_rw.2661254037
Short name T94
Test name
Test status
Simulation time 95089413 ps
CPU time 1.58 seconds
Started Mar 24 12:36:10 PM PDT 24
Finished Mar 24 12:36:12 PM PDT 24
Peak memory 218772 kb
Host smart-8df49192-96bd-4bb0-8f3c-7e13e2d47bb8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661254037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kma
c_shadow_reg_errors_with_csr_rw.2661254037 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_errors.58512370
Short name T1122
Test name
Test status
Simulation time 294090758 ps
CPU time 2.42 seconds
Started Mar 24 12:36:31 PM PDT 24
Finished Mar 24 12:36:33 PM PDT 24
Peak memory 216180 kb
Host smart-69328ccc-de20-4339-b10b-7c96ffc22f53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58512370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.58512370 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.kmac_tl_intg_err.1141148475
Short name T111
Test name
Test status
Simulation time 863232920 ps
CPU time 4.84 seconds
Started Mar 24 12:36:41 PM PDT 24
Finished Mar 24 12:36:48 PM PDT 24
Peak memory 216088 kb
Host smart-9b1aa909-2d9e-489f-9667-d6e24b73b2e6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141148475 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.1141
148475 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_mem_rw_with_rand_reset.864461382
Short name T1119
Test name
Test status
Simulation time 81004076 ps
CPU time 2.47 seconds
Started Mar 24 12:36:45 PM PDT 24
Finished Mar 24 12:36:48 PM PDT 24
Peak memory 221048 kb
Host smart-5a8ed026-ea29-4c71-98a4-cbb0050148f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864461382 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 16.kmac_csr_mem_rw_with_rand_reset.864461382 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_csr_rw.193102742
Short name T1100
Test name
Test status
Simulation time 22149392 ps
CPU time 1.11 seconds
Started Mar 24 12:36:42 PM PDT 24
Finished Mar 24 12:36:44 PM PDT 24
Peak memory 216128 kb
Host smart-e2312949-bb65-4631-8f93-7ac588a34603
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193102742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_csr_rw.193102742 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/16.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_intr_test.2322411765
Short name T1207
Test name
Test status
Simulation time 10969009 ps
CPU time 0.81 seconds
Started Mar 24 12:36:30 PM PDT 24
Finished Mar 24 12:36:32 PM PDT 24
Peak memory 216024 kb
Host smart-b47ee747-59e0-4f7e-a232-d853c31f46a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322411765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_intr_test.2322411765 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_same_csr_outstanding.223221340
Short name T135
Test name
Test status
Simulation time 487535301 ps
CPU time 2.86 seconds
Started Mar 24 12:36:34 PM PDT 24
Finished Mar 24 12:36:46 PM PDT 24
Peak memory 216172 kb
Host smart-2c36d9d2-8415-4b4d-8bc1-7deac4a288f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223221340 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_same_csr
_outstanding.223221340 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors.3350615830
Short name T1144
Test name
Test status
Simulation time 35156281 ps
CPU time 1.29 seconds
Started Mar 24 12:36:55 PM PDT 24
Finished Mar 24 12:36:57 PM PDT 24
Peak memory 216488 kb
Host smart-83c645b5-a592-476e-bb6d-ebc85e7570ed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350615830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg
_errors.3350615830 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_shadow_reg_errors_with_csr_rw.1796013723
Short name T1106
Test name
Test status
Simulation time 376129122 ps
CPU time 1.8 seconds
Started Mar 24 12:36:33 PM PDT 24
Finished Mar 24 12:36:35 PM PDT 24
Peak memory 218668 kb
Host smart-fd1d0fb5-42cb-4144-9f42-9bbde44895bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796013723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kma
c_shadow_reg_errors_with_csr_rw.1796013723 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.kmac_tl_errors.134668795
Short name T1190
Test name
Test status
Simulation time 228034369 ps
CPU time 1.87 seconds
Started Mar 24 12:36:42 PM PDT 24
Finished Mar 24 12:36:50 PM PDT 24
Peak memory 216176 kb
Host smart-e7c891b3-3591-46d3-b72b-e9859fe39a7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134668795 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.134668795 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/16.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_mem_rw_with_rand_reset.3567257387
Short name T1239
Test name
Test status
Simulation time 116422186 ps
CPU time 2.29 seconds
Started Mar 24 12:36:40 PM PDT 24
Finished Mar 24 12:36:45 PM PDT 24
Peak memory 222364 kb
Host smart-b9de0982-4ae9-4d9a-9961-23ea142ea826
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567257387 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 17.kmac_csr_mem_rw_with_rand_reset.3567257387 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_csr_rw.3124613550
Short name T153
Test name
Test status
Simulation time 33367876 ps
CPU time 1.13 seconds
Started Mar 24 12:36:24 PM PDT 24
Finished Mar 24 12:36:26 PM PDT 24
Peak memory 216220 kb
Host smart-52bd4417-344a-4b6d-b735-30cedbdd217c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124613550 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_csr_rw.3124613550 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_same_csr_outstanding.3212755749
Short name T1193
Test name
Test status
Simulation time 162199466 ps
CPU time 1.54 seconds
Started Mar 24 12:36:21 PM PDT 24
Finished Mar 24 12:36:23 PM PDT 24
Peak memory 216088 kb
Host smart-d1cacab3-253d-464c-af91-ab32019489d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212755749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_same_cs
r_outstanding.3212755749 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors.3417894808
Short name T1156
Test name
Test status
Simulation time 151360511 ps
CPU time 1.17 seconds
Started Mar 24 12:36:26 PM PDT 24
Finished Mar 24 12:36:31 PM PDT 24
Peak memory 216744 kb
Host smart-bcf1d471-d094-4cf0-bfac-0bc1186014d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417894808 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg
_errors.3417894808 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_shadow_reg_errors_with_csr_rw.687377967
Short name T1204
Test name
Test status
Simulation time 56017396 ps
CPU time 2.46 seconds
Started Mar 24 12:36:35 PM PDT 24
Finished Mar 24 12:36:38 PM PDT 24
Peak memory 220160 kb
Host smart-a92cdbf1-b993-49f4-9468-cb5b61069469
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=687377967 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_S
EQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac
_shadow_reg_errors_with_csr_rw.687377967 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_errors.4267194942
Short name T1176
Test name
Test status
Simulation time 78557913 ps
CPU time 1.46 seconds
Started Mar 24 12:36:33 PM PDT 24
Finished Mar 24 12:36:35 PM PDT 24
Peak memory 216160 kb
Host smart-c39bd056-42bb-448c-b38b-cb968a7ceea9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267194942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.4267194942 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.kmac_tl_intg_err.1930606743
Short name T1201
Test name
Test status
Simulation time 55947720 ps
CPU time 2.51 seconds
Started Mar 24 12:36:18 PM PDT 24
Finished Mar 24 12:36:20 PM PDT 24
Peak memory 216080 kb
Host smart-e9a1bb85-03e4-4dd4-b359-6a348a3fd49d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1930606743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.1930
606743 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_mem_rw_with_rand_reset.844366945
Short name T1167
Test name
Test status
Simulation time 147650462 ps
CPU time 2.5 seconds
Started Mar 24 12:36:35 PM PDT 24
Finished Mar 24 12:36:38 PM PDT 24
Peak memory 220780 kb
Host smart-5981eb57-71a6-4abd-b3ba-5ed40827f543
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=844366945 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 18.kmac_csr_mem_rw_with_rand_reset.844366945 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_csr_rw.2442938344
Short name T1237
Test name
Test status
Simulation time 45610765 ps
CPU time 0.97 seconds
Started Mar 24 12:37:03 PM PDT 24
Finished Mar 24 12:37:05 PM PDT 24
Peak memory 215888 kb
Host smart-4432426c-ba54-4ce2-a7c3-219d76f64b0d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442938344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_csr_rw.2442938344 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_intr_test.3073453669
Short name T1158
Test name
Test status
Simulation time 20568158 ps
CPU time 0.79 seconds
Started Mar 24 12:36:35 PM PDT 24
Finished Mar 24 12:36:36 PM PDT 24
Peak memory 215872 kb
Host smart-0f7ceee3-ebdf-479b-920e-2d56f2c2eb5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073453669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_intr_test.3073453669 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_same_csr_outstanding.2793833044
Short name T1164
Test name
Test status
Simulation time 800596948 ps
CPU time 2.41 seconds
Started Mar 24 12:36:28 PM PDT 24
Finished Mar 24 12:36:32 PM PDT 24
Peak memory 216104 kb
Host smart-08ac3389-3609-43d0-915d-74eb1f3c5e55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793833044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_same_cs
r_outstanding.2793833044 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors.690993207
Short name T1174
Test name
Test status
Simulation time 52640617 ps
CPU time 1.07 seconds
Started Mar 24 12:36:44 PM PDT 24
Finished Mar 24 12:36:45 PM PDT 24
Peak memory 216432 kb
Host smart-5cf0099b-ad35-4312-8eac-ebc17f448d28
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690993207 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_
errors.690993207 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_shadow_reg_errors_with_csr_rw.3539620742
Short name T88
Test name
Test status
Simulation time 424343746 ps
CPU time 2.64 seconds
Started Mar 24 12:36:31 PM PDT 24
Finished Mar 24 12:36:34 PM PDT 24
Peak memory 216448 kb
Host smart-949aae48-a8e2-4528-bc28-ddbc4b6a60b6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539620742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kma
c_shadow_reg_errors_with_csr_rw.3539620742 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_errors.4076465584
Short name T1217
Test name
Test status
Simulation time 49047541 ps
CPU time 2.27 seconds
Started Mar 24 12:36:17 PM PDT 24
Finished Mar 24 12:36:20 PM PDT 24
Peak memory 216160 kb
Host smart-56f184f9-b579-4c2c-877d-c1dde0d16b49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076465584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.4076465584 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.kmac_tl_intg_err.3295868027
Short name T1209
Test name
Test status
Simulation time 81596757 ps
CPU time 2.42 seconds
Started Mar 24 12:36:41 PM PDT 24
Finished Mar 24 12:36:46 PM PDT 24
Peak memory 216116 kb
Host smart-668c8013-a4da-40be-a009-bef841af8bb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295868027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.3295
868027 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_mem_rw_with_rand_reset.2965172096
Short name T1101
Test name
Test status
Simulation time 116627566 ps
CPU time 2.29 seconds
Started Mar 24 12:36:46 PM PDT 24
Finished Mar 24 12:36:48 PM PDT 24
Peak memory 221404 kb
Host smart-44efb5ad-0064-4b29-8531-0be1440b1f90
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965172096 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 19.kmac_csr_mem_rw_with_rand_reset.2965172096 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_csr_rw.1795466772
Short name T1099
Test name
Test status
Simulation time 308453570 ps
CPU time 1.01 seconds
Started Mar 24 12:36:34 PM PDT 24
Finished Mar 24 12:36:36 PM PDT 24
Peak memory 215944 kb
Host smart-5fe6be14-fd23-4f26-b686-1d5d19347c21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795466772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_csr_rw.1795466772 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_intr_test.2575630243
Short name T1234
Test name
Test status
Simulation time 17695206 ps
CPU time 0.82 seconds
Started Mar 24 12:36:29 PM PDT 24
Finished Mar 24 12:36:31 PM PDT 24
Peak memory 215976 kb
Host smart-f3fb9c21-b703-4a82-a42e-91a5e5c8a07d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575630243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_intr_test.2575630243 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_same_csr_outstanding.366825742
Short name T1114
Test name
Test status
Simulation time 27961038 ps
CPU time 1.54 seconds
Started Mar 24 12:36:41 PM PDT 24
Finished Mar 24 12:36:45 PM PDT 24
Peak memory 216112 kb
Host smart-f57eead1-2ec2-42b7-8fb9-c5f8242fa015
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366825742 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_same_csr
_outstanding.366825742 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors.3469168678
Short name T1229
Test name
Test status
Simulation time 68838922 ps
CPU time 1.11 seconds
Started Mar 24 12:36:28 PM PDT 24
Finished Mar 24 12:36:31 PM PDT 24
Peak memory 216460 kb
Host smart-a47084e6-e013-4ba8-984e-bf7a5902bdcf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469168678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg
_errors.3469168678 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_shadow_reg_errors_with_csr_rw.26365463
Short name T1134
Test name
Test status
Simulation time 393947214 ps
CPU time 2.7 seconds
Started Mar 24 12:36:43 PM PDT 24
Finished Mar 24 12:36:46 PM PDT 24
Peak memory 216460 kb
Host smart-16494e33-4fa6-4a9f-ac3c-e756f19dc111
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26365463 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_
shadow_reg_errors_with_csr_rw.26365463 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.kmac_tl_errors.988748889
Short name T1227
Test name
Test status
Simulation time 273268394 ps
CPU time 1.94 seconds
Started Mar 24 12:36:33 PM PDT 24
Finished Mar 24 12:36:35 PM PDT 24
Peak memory 216188 kb
Host smart-0a6e0dd5-a72b-405c-af63-d1143382464a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988748889 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.988748889 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/19.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_aliasing.937695005
Short name T1087
Test name
Test status
Simulation time 79911429 ps
CPU time 4.55 seconds
Started Mar 24 12:36:21 PM PDT 24
Finished Mar 24 12:36:26 PM PDT 24
Peak memory 216104 kb
Host smart-4b930f83-040f-4b16-bc2e-f3bb4ca8c726
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937695005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_aliasing.93769500
5 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_bit_bash.2630144549
Short name T1203
Test name
Test status
Simulation time 2537272605 ps
CPU time 18.87 seconds
Started Mar 24 12:36:14 PM PDT 24
Finished Mar 24 12:36:33 PM PDT 24
Peak memory 216212 kb
Host smart-1ed3b798-4729-491b-896b-495bf7899a32
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630144549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_bit_bash.2630144
549 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_hw_reset.1756723307
Short name T1242
Test name
Test status
Simulation time 31809285 ps
CPU time 1.05 seconds
Started Mar 24 12:35:59 PM PDT 24
Finished Mar 24 12:36:00 PM PDT 24
Peak memory 216120 kb
Host smart-0d964b2f-827e-4546-8442-84d3c804139e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756723307 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_hw_reset.1756723
307 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_mem_rw_with_rand_reset.905196629
Short name T1141
Test name
Test status
Simulation time 48293156 ps
CPU time 1.79 seconds
Started Mar 24 12:36:22 PM PDT 24
Finished Mar 24 12:36:25 PM PDT 24
Peak memory 217404 kb
Host smart-815b6e34-b694-4a49-9747-be7601e73010
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905196629 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.905196629 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_csr_rw.990508787
Short name T1186
Test name
Test status
Simulation time 24024881 ps
CPU time 1.16 seconds
Started Mar 24 12:36:14 PM PDT 24
Finished Mar 24 12:36:15 PM PDT 24
Peak memory 216124 kb
Host smart-2c929092-bfa8-4bf3-aacb-8716096891a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990508787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.990508787 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/2.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_intr_test.2219249321
Short name T162
Test name
Test status
Simulation time 17771490 ps
CPU time 0.82 seconds
Started Mar 24 12:36:20 PM PDT 24
Finished Mar 24 12:36:24 PM PDT 24
Peak memory 215948 kb
Host smart-c17c70b6-ed5b-4ef4-908f-4f1794a14259
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219249321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.2219249321 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_partial_access.117602243
Short name T126
Test name
Test status
Simulation time 231940878 ps
CPU time 1.2 seconds
Started Mar 24 12:36:22 PM PDT 24
Finished Mar 24 12:36:24 PM PDT 24
Peak memory 216108 kb
Host smart-48dccd05-4456-41fe-89cc-1cc7b1b3032d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117602243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_partial
_access.117602243 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_mem_walk.24891758
Short name T1131
Test name
Test status
Simulation time 32086069 ps
CPU time 0.77 seconds
Started Mar 24 12:36:18 PM PDT 24
Finished Mar 24 12:36:19 PM PDT 24
Peak memory 215924 kb
Host smart-f9e3726b-3420-40ee-bf02-df514780aaf2
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24891758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_mem_walk.24891758 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_same_csr_outstanding.3788481611
Short name T1180
Test name
Test status
Simulation time 227932106 ps
CPU time 1.56 seconds
Started Mar 24 12:36:33 PM PDT 24
Finished Mar 24 12:36:35 PM PDT 24
Peak memory 216124 kb
Host smart-62e3c1de-0552-4f7d-9936-b8a62bfefeff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788481611 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr
_outstanding.3788481611 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_shadow_reg_errors_with_csr_rw.3905015994
Short name T1188
Test name
Test status
Simulation time 241270426 ps
CPU time 1.86 seconds
Started Mar 24 12:36:12 PM PDT 24
Finished Mar 24 12:36:14 PM PDT 24
Peak memory 216500 kb
Host smart-41a917fe-4cbd-4e96-94c7-48acf67b76d8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905015994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac
_shadow_reg_errors_with_csr_rw.3905015994 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_errors.3457851386
Short name T1232
Test name
Test status
Simulation time 102854157 ps
CPU time 1.87 seconds
Started Mar 24 12:36:23 PM PDT 24
Finished Mar 24 12:36:27 PM PDT 24
Peak memory 216192 kb
Host smart-db5375db-486b-482d-bcbf-7adb531dc37c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457851386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.3457851386 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.kmac_tl_intg_err.1450966697
Short name T169
Test name
Test status
Simulation time 213033691 ps
CPU time 4.5 seconds
Started Mar 24 12:36:14 PM PDT 24
Finished Mar 24 12:36:19 PM PDT 24
Peak memory 216112 kb
Host smart-5bd732c8-2f72-472e-b3bc-da4793f2644e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450966697 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.14509
66697 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.kmac_intr_test.1312448049
Short name T1154
Test name
Test status
Simulation time 88797489 ps
CPU time 0.8 seconds
Started Mar 24 12:36:43 PM PDT 24
Finished Mar 24 12:36:44 PM PDT 24
Peak memory 215908 kb
Host smart-899a4478-e69d-4610-bba3-4b4ce0d3f745
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312448049 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_intr_test.1312448049 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.kmac_intr_test.2729571864
Short name T159
Test name
Test status
Simulation time 16826732 ps
CPU time 0.81 seconds
Started Mar 24 12:36:51 PM PDT 24
Finished Mar 24 12:36:52 PM PDT 24
Peak memory 215872 kb
Host smart-2a52c0da-8f8a-45fb-b165-8792c30ab488
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729571864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_intr_test.2729571864 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.kmac_intr_test.3256181681
Short name T1169
Test name
Test status
Simulation time 40296133 ps
CPU time 0.8 seconds
Started Mar 24 12:36:16 PM PDT 24
Finished Mar 24 12:36:18 PM PDT 24
Peak memory 215944 kb
Host smart-9beb3d2c-4522-4cee-9bf6-a56b569e6627
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256181681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_intr_test.3256181681 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.kmac_intr_test.158226318
Short name T1107
Test name
Test status
Simulation time 15554124 ps
CPU time 0.79 seconds
Started Mar 24 12:36:25 PM PDT 24
Finished Mar 24 12:36:28 PM PDT 24
Peak memory 215908 kb
Host smart-7c2f5bba-bac1-4140-9979-25805520e0c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158226318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_intr_test.158226318 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/23.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.kmac_intr_test.2966644567
Short name T1241
Test name
Test status
Simulation time 47973885 ps
CPU time 0.79 seconds
Started Mar 24 12:36:41 PM PDT 24
Finished Mar 24 12:36:44 PM PDT 24
Peak memory 215956 kb
Host smart-1614194f-423f-4ead-844f-4c4abf4366e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966644567 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_intr_test.2966644567 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.kmac_intr_test.2674687310
Short name T1211
Test name
Test status
Simulation time 17291944 ps
CPU time 0.79 seconds
Started Mar 24 12:36:42 PM PDT 24
Finished Mar 24 12:36:44 PM PDT 24
Peak memory 215916 kb
Host smart-c8005a05-92bf-48eb-8019-5a9894f119d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674687310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.kmac_intr_test.2674687310 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.kmac_intr_test.2067869596
Short name T1112
Test name
Test status
Simulation time 49191573 ps
CPU time 0.77 seconds
Started Mar 24 12:36:47 PM PDT 24
Finished Mar 24 12:36:48 PM PDT 24
Peak memory 215908 kb
Host smart-889ded4f-be12-450c-be3d-86ecea41be35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067869596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.kmac_intr_test.2067869596 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.kmac_intr_test.2342554255
Short name T1118
Test name
Test status
Simulation time 29761944 ps
CPU time 0.77 seconds
Started Mar 24 12:36:41 PM PDT 24
Finished Mar 24 12:36:44 PM PDT 24
Peak memory 215720 kb
Host smart-e5f8e899-3056-406c-8f0c-aa903032c3d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342554255 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.kmac_intr_test.2342554255 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.kmac_intr_test.2378135438
Short name T1139
Test name
Test status
Simulation time 82096616 ps
CPU time 0.8 seconds
Started Mar 24 12:36:36 PM PDT 24
Finished Mar 24 12:36:37 PM PDT 24
Peak memory 215936 kb
Host smart-f5ca9fe3-bc94-4c5e-aade-12c536ad61f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378135438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.kmac_intr_test.2378135438 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.kmac_intr_test.224346128
Short name T1235
Test name
Test status
Simulation time 98036354 ps
CPU time 0.84 seconds
Started Mar 24 12:36:52 PM PDT 24
Finished Mar 24 12:36:54 PM PDT 24
Peak memory 215884 kb
Host smart-5227e85e-54ec-4283-a86f-88977f4bde06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224346128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.kmac_intr_test.224346128 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/29.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_aliasing.3893193477
Short name T1161
Test name
Test status
Simulation time 1018994060 ps
CPU time 5.23 seconds
Started Mar 24 12:36:21 PM PDT 24
Finished Mar 24 12:36:27 PM PDT 24
Peak memory 216152 kb
Host smart-ff4129e4-01f9-4d95-8811-192804e8cb92
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893193477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_aliasing.3893193
477 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_bit_bash.4249268713
Short name T136
Test name
Test status
Simulation time 8478737626 ps
CPU time 21.86 seconds
Started Mar 24 12:36:18 PM PDT 24
Finished Mar 24 12:36:40 PM PDT 24
Peak memory 216204 kb
Host smart-3b573bd1-8361-444c-8f15-e2077e85844c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249268713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_bit_bash.4249268
713 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_hw_reset.1165826050
Short name T1195
Test name
Test status
Simulation time 98844379 ps
CPU time 1.18 seconds
Started Mar 24 12:36:23 PM PDT 24
Finished Mar 24 12:36:24 PM PDT 24
Peak memory 216164 kb
Host smart-eabec5b5-6444-4448-bae4-bdacef416c10
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165826050 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_hw_reset.1165826
050 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_mem_rw_with_rand_reset.2806573771
Short name T1095
Test name
Test status
Simulation time 90539385 ps
CPU time 1.79 seconds
Started Mar 24 12:36:27 PM PDT 24
Finished Mar 24 12:36:31 PM PDT 24
Peak memory 217708 kb
Host smart-e5d7d549-b8ec-4609-86f4-5207c5d5d5f8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806573771 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.2806573771 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_csr_rw.1957821551
Short name T138
Test name
Test status
Simulation time 44676612 ps
CPU time 0.95 seconds
Started Mar 24 12:36:21 PM PDT 24
Finished Mar 24 12:36:23 PM PDT 24
Peak memory 215964 kb
Host smart-bf534188-d506-41d2-835d-121e9bf310f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957821551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.1957821551 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_intr_test.4187527507
Short name T1214
Test name
Test status
Simulation time 44782841 ps
CPU time 0.8 seconds
Started Mar 24 12:36:44 PM PDT 24
Finished Mar 24 12:36:45 PM PDT 24
Peak memory 215948 kb
Host smart-f282ed64-745e-43d7-825e-6b9a08098b90
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187527507 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.4187527507 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_partial_access.2930226856
Short name T125
Test name
Test status
Simulation time 18451690 ps
CPU time 1.36 seconds
Started Mar 24 12:36:13 PM PDT 24
Finished Mar 24 12:36:14 PM PDT 24
Peak memory 216140 kb
Host smart-8e38dce4-f4a9-4177-893b-f93b3401b51a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930226856 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_partia
l_access.2930226856 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_mem_walk.2445234193
Short name T1097
Test name
Test status
Simulation time 32527512 ps
CPU time 0.77 seconds
Started Mar 24 12:36:19 PM PDT 24
Finished Mar 24 12:36:20 PM PDT 24
Peak memory 215900 kb
Host smart-a66e658c-9565-4ec6-8478-2bf59f7503f4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445234193 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_mem_walk.2445234193
+enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_same_csr_outstanding.1321348316
Short name T1218
Test name
Test status
Simulation time 107762666 ps
CPU time 1.46 seconds
Started Mar 24 12:36:13 PM PDT 24
Finished Mar 24 12:36:15 PM PDT 24
Peak memory 216140 kb
Host smart-9bdcfac8-28c9-431a-8ebb-6ef134a0ab54
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321348316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr
_outstanding.1321348316 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors.3031900877
Short name T1225
Test name
Test status
Simulation time 107331934 ps
CPU time 1.13 seconds
Started Mar 24 12:36:26 PM PDT 24
Finished Mar 24 12:36:28 PM PDT 24
Peak memory 216184 kb
Host smart-428d0573-89da-4ed3-b01f-8da5fdf5a580
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031900877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_
errors.3031900877 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_shadow_reg_errors_with_csr_rw.3915386803
Short name T89
Test name
Test status
Simulation time 738782842 ps
CPU time 2.43 seconds
Started Mar 24 12:36:32 PM PDT 24
Finished Mar 24 12:36:36 PM PDT 24
Peak memory 216168 kb
Host smart-33bc9f66-1cbf-41b6-9231-3101950fac72
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915386803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac
_shadow_reg_errors_with_csr_rw.3915386803 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_errors.1378704805
Short name T1221
Test name
Test status
Simulation time 117960009 ps
CPU time 1.88 seconds
Started Mar 24 12:36:08 PM PDT 24
Finished Mar 24 12:36:10 PM PDT 24
Peak memory 216212 kb
Host smart-38b5a711-02b3-4564-9bfc-443768b14b6c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378704805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.1378704805 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.kmac_tl_intg_err.41637141
Short name T172
Test name
Test status
Simulation time 374123536 ps
CPU time 4.71 seconds
Started Mar 24 12:36:19 PM PDT 24
Finished Mar 24 12:36:28 PM PDT 24
Peak memory 216116 kb
Host smart-a12122ec-f855-4a93-92ee-ab5ed6aa6dad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41637141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.4163714
1 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.kmac_intr_test.3987835994
Short name T1102
Test name
Test status
Simulation time 15057666 ps
CPU time 0.77 seconds
Started Mar 24 12:36:47 PM PDT 24
Finished Mar 24 12:36:48 PM PDT 24
Peak memory 215896 kb
Host smart-95eb875c-52c9-4522-a2bf-52c8d2c0719b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987835994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.kmac_intr_test.3987835994 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.kmac_intr_test.2929411517
Short name T1120
Test name
Test status
Simulation time 21665881 ps
CPU time 0.78 seconds
Started Mar 24 12:36:25 PM PDT 24
Finished Mar 24 12:36:26 PM PDT 24
Peak memory 215928 kb
Host smart-c18af334-a0ee-48ec-8696-850f44824d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929411517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.kmac_intr_test.2929411517 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.kmac_intr_test.980349372
Short name T115
Test name
Test status
Simulation time 20532625 ps
CPU time 0.8 seconds
Started Mar 24 12:36:35 PM PDT 24
Finished Mar 24 12:36:36 PM PDT 24
Peak memory 215912 kb
Host smart-78da3a0e-ff6e-4122-b7e1-ae8e6eef70c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980349372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.kmac_intr_test.980349372 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/32.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.kmac_intr_test.671685568
Short name T161
Test name
Test status
Simulation time 23376258 ps
CPU time 0.79 seconds
Started Mar 24 12:36:37 PM PDT 24
Finished Mar 24 12:36:42 PM PDT 24
Peak memory 215924 kb
Host smart-69480c87-4d37-428b-b044-6c36af9e0d7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671685568 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.kmac_intr_test.671685568 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/33.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.kmac_intr_test.1116248116
Short name T1159
Test name
Test status
Simulation time 28316050 ps
CPU time 0.82 seconds
Started Mar 24 12:36:35 PM PDT 24
Finished Mar 24 12:36:37 PM PDT 24
Peak memory 215908 kb
Host smart-04f38011-5e22-40bb-8296-94dfc47fd289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1116248116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.kmac_intr_test.1116248116 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.kmac_intr_test.4247944411
Short name T1109
Test name
Test status
Simulation time 11442696 ps
CPU time 0.8 seconds
Started Mar 24 12:36:22 PM PDT 24
Finished Mar 24 12:36:24 PM PDT 24
Peak memory 215892 kb
Host smart-3dbf9854-7c61-4e0f-acc1-405c9640ec5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247944411 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.kmac_intr_test.4247944411 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.kmac_intr_test.3544472379
Short name T116
Test name
Test status
Simulation time 12509063 ps
CPU time 0.77 seconds
Started Mar 24 12:36:21 PM PDT 24
Finished Mar 24 12:36:22 PM PDT 24
Peak memory 215920 kb
Host smart-561ef807-266c-4df4-8cab-0de93102fd82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544472379 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.kmac_intr_test.3544472379 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.kmac_intr_test.156954404
Short name T1233
Test name
Test status
Simulation time 22676982 ps
CPU time 0.77 seconds
Started Mar 24 12:36:28 PM PDT 24
Finished Mar 24 12:36:44 PM PDT 24
Peak memory 215908 kb
Host smart-264023af-9a7b-49ce-8957-1780dbc299fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156954404 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.kmac_intr_test.156954404 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/37.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.kmac_intr_test.2927833675
Short name T1123
Test name
Test status
Simulation time 73337677 ps
CPU time 0.83 seconds
Started Mar 24 12:36:44 PM PDT 24
Finished Mar 24 12:36:45 PM PDT 24
Peak memory 215924 kb
Host smart-ff7a2bc9-0a2d-4387-9c74-33d197ac6f59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927833675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.kmac_intr_test.2927833675 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_aliasing.1409898317
Short name T1129
Test name
Test status
Simulation time 290673303 ps
CPU time 4.59 seconds
Started Mar 24 12:36:09 PM PDT 24
Finished Mar 24 12:36:14 PM PDT 24
Peak memory 216144 kb
Host smart-3c005f9f-b8cf-4e0e-a8cb-eb53fcc37172
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409898317 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_aliasing.1409898
317 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_bit_bash.427880290
Short name T1240
Test name
Test status
Simulation time 1498342991 ps
CPU time 10.99 seconds
Started Mar 24 12:36:22 PM PDT 24
Finished Mar 24 12:36:34 PM PDT 24
Peak memory 216136 kb
Host smart-ea3c3e45-6f9f-4d94-8353-20323064658c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427880290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_bit_bash.42788029
0 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_hw_reset.4261998129
Short name T1187
Test name
Test status
Simulation time 18777559 ps
CPU time 1.1 seconds
Started Mar 24 12:36:10 PM PDT 24
Finished Mar 24 12:36:12 PM PDT 24
Peak memory 216148 kb
Host smart-8f23b56a-ddd0-4ad0-b03d-870fa768fc5a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261998129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_hw_reset.4261998
129 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_mem_rw_with_rand_reset.643325047
Short name T174
Test name
Test status
Simulation time 64899666 ps
CPU time 2.42 seconds
Started Mar 24 12:36:23 PM PDT 24
Finished Mar 24 12:36:25 PM PDT 24
Peak memory 222356 kb
Host smart-87831793-fe5f-4cbc-8a7e-09ad7e5314a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643325047 -assert nopostproc +UVM_TESTNAME=
kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.643325047 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_csr_rw.1492835214
Short name T1091
Test name
Test status
Simulation time 22229734 ps
CPU time 0.94 seconds
Started Mar 24 12:36:09 PM PDT 24
Finished Mar 24 12:36:10 PM PDT 24
Peak memory 215948 kb
Host smart-5e8caf11-ea11-48ed-9cf3-751b9e6d9d2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492835214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.1492835214 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_intr_test.2978767213
Short name T1136
Test name
Test status
Simulation time 27917531 ps
CPU time 0.8 seconds
Started Mar 24 12:36:10 PM PDT 24
Finished Mar 24 12:36:11 PM PDT 24
Peak memory 215940 kb
Host smart-475b912d-8cd9-4a4b-af35-a884665fe94f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978767213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.2978767213 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_partial_access.2755973068
Short name T128
Test name
Test status
Simulation time 68687080 ps
CPU time 1.37 seconds
Started Mar 24 12:36:21 PM PDT 24
Finished Mar 24 12:36:26 PM PDT 24
Peak memory 216096 kb
Host smart-0e19aca6-082c-49de-a11a-8052a3297e3c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755973068 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_partia
l_access.2755973068 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_mem_walk.4212996527
Short name T1194
Test name
Test status
Simulation time 23628686 ps
CPU time 0.73 seconds
Started Mar 24 12:36:29 PM PDT 24
Finished Mar 24 12:36:31 PM PDT 24
Peak memory 216028 kb
Host smart-db07fb49-3201-4d8b-8076-4cab91411b38
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212996527 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_mem_walk.4212996527
+enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_same_csr_outstanding.1746135855
Short name T1208
Test name
Test status
Simulation time 51410826 ps
CPU time 1.65 seconds
Started Mar 24 12:36:21 PM PDT 24
Finished Mar 24 12:36:23 PM PDT 24
Peak memory 216140 kb
Host smart-c8370d3d-7375-488c-bade-b7e12c8fdabc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746135855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr
_outstanding.1746135855 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors.3352968437
Short name T96
Test name
Test status
Simulation time 68101210 ps
CPU time 1.11 seconds
Started Mar 24 12:36:18 PM PDT 24
Finished Mar 24 12:36:19 PM PDT 24
Peak memory 216640 kb
Host smart-90e19f79-ce47-4f56-bd63-264d1d6cf342
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352968437 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_
errors.3352968437 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_shadow_reg_errors_with_csr_rw.85171601
Short name T87
Test name
Test status
Simulation time 232766725 ps
CPU time 1.68 seconds
Started Mar 24 12:36:02 PM PDT 24
Finished Mar 24 12:36:04 PM PDT 24
Peak memory 216484 kb
Host smart-9ce980ed-e291-43f0-b73a-f8bae1eb2d1e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85171601 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SE
Q=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_s
hadow_reg_errors_with_csr_rw.85171601 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_errors.962718214
Short name T1196
Test name
Test status
Simulation time 1774145877 ps
CPU time 3.25 seconds
Started Mar 24 12:36:20 PM PDT 24
Finished Mar 24 12:36:23 PM PDT 24
Peak memory 216220 kb
Host smart-9ae2b145-3bf5-4191-8db9-9fe6f79c7344
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962718214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.962718214 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.kmac_tl_intg_err.2824186575
Short name T1226
Test name
Test status
Simulation time 97813421 ps
CPU time 2.29 seconds
Started Mar 24 12:36:34 PM PDT 24
Finished Mar 24 12:36:37 PM PDT 24
Peak memory 216120 kb
Host smart-0cb3cd71-79bc-4121-90d9-6d04f68b8040
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824186575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.28241
86575 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.kmac_intr_test.1035048997
Short name T1147
Test name
Test status
Simulation time 38903666 ps
CPU time 0.76 seconds
Started Mar 24 12:36:39 PM PDT 24
Finished Mar 24 12:36:44 PM PDT 24
Peak memory 215916 kb
Host smart-2c37acc9-24c5-47ef-942c-8b28487e64f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035048997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.kmac_intr_test.1035048997 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.kmac_intr_test.2043943907
Short name T157
Test name
Test status
Simulation time 37225161 ps
CPU time 0.77 seconds
Started Mar 24 12:36:22 PM PDT 24
Finished Mar 24 12:36:24 PM PDT 24
Peak memory 215912 kb
Host smart-88484639-a4b2-49b1-a5eb-5e9f5a4e6559
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043943907 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.kmac_intr_test.2043943907 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.kmac_intr_test.78622176
Short name T1115
Test name
Test status
Simulation time 53095214 ps
CPU time 0.78 seconds
Started Mar 24 12:36:19 PM PDT 24
Finished Mar 24 12:36:20 PM PDT 24
Peak memory 215912 kb
Host smart-9baaa8c3-4c07-44f2-bb9d-f1de737f768b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78622176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.kmac_intr_test.78622176 +enable_mas
king=1 +sw_key_masked=0
Directory /workspace/42.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.kmac_intr_test.3502650398
Short name T1090
Test name
Test status
Simulation time 39040246 ps
CPU time 0.82 seconds
Started Mar 24 12:36:27 PM PDT 24
Finished Mar 24 12:36:30 PM PDT 24
Peak memory 215840 kb
Host smart-0e22fe7d-a1ed-4571-b0e0-f8bea9069649
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502650398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.kmac_intr_test.3502650398 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.kmac_intr_test.1343871522
Short name T1111
Test name
Test status
Simulation time 12493263 ps
CPU time 0.77 seconds
Started Mar 24 12:36:45 PM PDT 24
Finished Mar 24 12:36:46 PM PDT 24
Peak memory 215908 kb
Host smart-27679fee-2a33-48aa-926a-cda1d2a9bc31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343871522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.kmac_intr_test.1343871522 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.kmac_intr_test.2867061230
Short name T1171
Test name
Test status
Simulation time 26905348 ps
CPU time 0.79 seconds
Started Mar 24 12:36:24 PM PDT 24
Finished Mar 24 12:36:26 PM PDT 24
Peak memory 215928 kb
Host smart-009bffa5-1486-44e3-a023-ed6cd89bf3c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867061230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.kmac_intr_test.2867061230 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.kmac_intr_test.659934531
Short name T158
Test name
Test status
Simulation time 15522941 ps
CPU time 0.78 seconds
Started Mar 24 12:36:33 PM PDT 24
Finished Mar 24 12:36:34 PM PDT 24
Peak memory 215948 kb
Host smart-7c30b56c-1c6a-44af-bcee-26dbf7045d72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659934531 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.kmac_intr_test.659934531 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/46.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.kmac_intr_test.1940437798
Short name T1104
Test name
Test status
Simulation time 15333869 ps
CPU time 0.79 seconds
Started Mar 24 12:36:34 PM PDT 24
Finished Mar 24 12:36:36 PM PDT 24
Peak memory 215952 kb
Host smart-9196a5c2-6d07-4cac-8497-d1326a307281
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940437798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.kmac_intr_test.1940437798 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.kmac_intr_test.3471975785
Short name T156
Test name
Test status
Simulation time 42231520 ps
CPU time 0.77 seconds
Started Mar 24 12:36:20 PM PDT 24
Finished Mar 24 12:36:21 PM PDT 24
Peak memory 215892 kb
Host smart-a584d065-1c09-4eb2-a9de-e2b690774e6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471975785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.kmac_intr_test.3471975785 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.kmac_intr_test.2363129268
Short name T1151
Test name
Test status
Simulation time 16679145 ps
CPU time 0.84 seconds
Started Mar 24 12:36:45 PM PDT 24
Finished Mar 24 12:36:45 PM PDT 24
Peak memory 215944 kb
Host smart-02f097d7-4071-4ae7-b338-8935bf36b8c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363129268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.kmac_intr_test.2363129268 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_mem_rw_with_rand_reset.2853738385
Short name T1223
Test name
Test status
Simulation time 182260426 ps
CPU time 2.23 seconds
Started Mar 24 12:37:12 PM PDT 24
Finished Mar 24 12:37:14 PM PDT 24
Peak memory 220832 kb
Host smart-39100b47-8291-4ac7-9168-5fdb6da961e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853738385 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 5.kmac_csr_mem_rw_with_rand_reset.2853738385 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_csr_rw.152411981
Short name T1173
Test name
Test status
Simulation time 103502526 ps
CPU time 1.05 seconds
Started Mar 24 12:36:40 PM PDT 24
Finished Mar 24 12:36:44 PM PDT 24
Peak memory 215920 kb
Host smart-abe77265-c4b3-4a79-8dff-0566c92ba1ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152411981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_csr_rw.152411981 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/5.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_intr_test.3624228215
Short name T1184
Test name
Test status
Simulation time 12389727 ps
CPU time 0.79 seconds
Started Mar 24 12:36:23 PM PDT 24
Finished Mar 24 12:36:24 PM PDT 24
Peak memory 215924 kb
Host smart-58b4da17-054f-4547-beaf-1fea4fc5bdc8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624228215 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.3624228215 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_same_csr_outstanding.1476192272
Short name T1089
Test name
Test status
Simulation time 28431337 ps
CPU time 1.54 seconds
Started Mar 24 12:36:19 PM PDT 24
Finished Mar 24 12:36:21 PM PDT 24
Peak memory 216148 kb
Host smart-a60a02c8-dc89-446f-b20a-c2ffba049c23
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476192272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_same_csr
_outstanding.1476192272 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors.1619919571
Short name T86
Test name
Test status
Simulation time 594755340 ps
CPU time 1.42 seconds
Started Mar 24 12:36:11 PM PDT 24
Finished Mar 24 12:36:12 PM PDT 24
Peak memory 216428 kb
Host smart-11e28f0d-aaad-4737-9ea4-53d169a3d4fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619919571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_
errors.1619919571 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_shadow_reg_errors_with_csr_rw.4083854112
Short name T1243
Test name
Test status
Simulation time 379329845 ps
CPU time 1.9 seconds
Started Mar 24 12:36:46 PM PDT 24
Finished Mar 24 12:36:47 PM PDT 24
Peak memory 219356 kb
Host smart-0c2ba401-df68-4343-9539-530261cd888c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083854112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac
_shadow_reg_errors_with_csr_rw.4083854112 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_errors.345989630
Short name T1110
Test name
Test status
Simulation time 100405392 ps
CPU time 1.63 seconds
Started Mar 24 12:36:29 PM PDT 24
Finished Mar 24 12:36:32 PM PDT 24
Peak memory 216192 kb
Host smart-f71c4f02-2862-4f5e-972b-3a3a3ed5e848
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345989630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.345989630 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.kmac_tl_intg_err.1950782657
Short name T166
Test name
Test status
Simulation time 402172382 ps
CPU time 2.9 seconds
Started Mar 24 12:36:27 PM PDT 24
Finished Mar 24 12:36:32 PM PDT 24
Peak memory 216128 kb
Host smart-0ea725de-6829-4917-8b1d-c07ae91b1177
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950782657 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.19507
82657 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_mem_rw_with_rand_reset.3867860698
Short name T1222
Test name
Test status
Simulation time 90149778 ps
CPU time 1.76 seconds
Started Mar 24 12:36:09 PM PDT 24
Finished Mar 24 12:36:11 PM PDT 24
Peak memory 221796 kb
Host smart-2cf984ba-4b6a-448a-b59d-b21a35525f07
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867860698 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 6.kmac_csr_mem_rw_with_rand_reset.3867860698 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_csr_rw.587669318
Short name T139
Test name
Test status
Simulation time 23124807 ps
CPU time 0.96 seconds
Started Mar 24 12:36:21 PM PDT 24
Finished Mar 24 12:36:24 PM PDT 24
Peak memory 215920 kb
Host smart-f37ce737-ec09-437b-8d75-b08979eca37d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587669318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_csr_rw.587669318 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/6.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_intr_test.4007463435
Short name T1127
Test name
Test status
Simulation time 43910392 ps
CPU time 0.81 seconds
Started Mar 24 12:36:41 PM PDT 24
Finished Mar 24 12:36:44 PM PDT 24
Peak memory 215892 kb
Host smart-9f9f3779-30f8-4e7c-8a46-466c073731ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007463435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.4007463435 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_same_csr_outstanding.10390386
Short name T1138
Test name
Test status
Simulation time 125947681 ps
CPU time 2.53 seconds
Started Mar 24 12:36:37 PM PDT 24
Finished Mar 24 12:36:39 PM PDT 24
Peak memory 216108 kb
Host smart-c3cfb25d-e0b4-4b8c-ac3d-084882788524
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10390386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_same_csr_o
utstanding.10390386 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors.603207322
Short name T1224
Test name
Test status
Simulation time 45542520 ps
CPU time 1.19 seconds
Started Mar 24 12:36:22 PM PDT 24
Finished Mar 24 12:36:24 PM PDT 24
Peak memory 216520 kb
Host smart-d6397525-a7ea-4d05-84be-021ccf64cf9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603207322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_e
rrors.603207322 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_shadow_reg_errors_with_csr_rw.1560362912
Short name T92
Test name
Test status
Simulation time 58472561 ps
CPU time 1.71 seconds
Started Mar 24 12:36:35 PM PDT 24
Finished Mar 24 12:36:37 PM PDT 24
Peak memory 219056 kb
Host smart-ec78690e-d964-4ac4-9c1d-e770b541cb2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560362912 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac
_shadow_reg_errors_with_csr_rw.1560362912 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.kmac_tl_errors.3775543344
Short name T1094
Test name
Test status
Simulation time 214424631 ps
CPU time 2.83 seconds
Started Mar 24 12:36:09 PM PDT 24
Finished Mar 24 12:36:12 PM PDT 24
Peak memory 216256 kb
Host smart-ba8a7032-aaef-4cc9-90d3-076601b67775
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775543344 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.3775543344 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_mem_rw_with_rand_reset.3661054375
Short name T140
Test name
Test status
Simulation time 174147462 ps
CPU time 1.62 seconds
Started Mar 24 12:36:33 PM PDT 24
Finished Mar 24 12:36:35 PM PDT 24
Peak memory 217272 kb
Host smart-44dfe15d-6a0d-4966-a13d-ff06a7164a5f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661054375 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 7.kmac_csr_mem_rw_with_rand_reset.3661054375 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_csr_rw.1531380254
Short name T1124
Test name
Test status
Simulation time 39138299 ps
CPU time 1 seconds
Started Mar 24 12:36:40 PM PDT 24
Finished Mar 24 12:36:44 PM PDT 24
Peak memory 215948 kb
Host smart-423ba7ad-242e-4f23-bf68-5c43bbdb2da2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531380254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_csr_rw.1531380254 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_intr_test.3682915648
Short name T1121
Test name
Test status
Simulation time 32917868 ps
CPU time 0.77 seconds
Started Mar 24 12:36:21 PM PDT 24
Finished Mar 24 12:36:23 PM PDT 24
Peak memory 215884 kb
Host smart-432ee116-15a7-493b-9735-41df6c2d78e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682915648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.3682915648 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_same_csr_outstanding.950384970
Short name T1220
Test name
Test status
Simulation time 101691179 ps
CPU time 2.38 seconds
Started Mar 24 12:36:32 PM PDT 24
Finished Mar 24 12:36:35 PM PDT 24
Peak memory 216156 kb
Host smart-d6593b2c-0e6b-46e1-befa-1a45c42905ed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950384970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_same_csr_
outstanding.950384970 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors.1854863577
Short name T1132
Test name
Test status
Simulation time 76934108 ps
CPU time 1.1 seconds
Started Mar 24 12:36:27 PM PDT 24
Finished Mar 24 12:36:31 PM PDT 24
Peak memory 216460 kb
Host smart-71aee685-0bbe-4d1c-84dc-fb5edc789db1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854863577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_
errors.1854863577 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_shadow_reg_errors_with_csr_rw.3174521396
Short name T1206
Test name
Test status
Simulation time 544219325 ps
CPU time 1.98 seconds
Started Mar 24 12:36:10 PM PDT 24
Finished Mar 24 12:36:13 PM PDT 24
Peak memory 219876 kb
Host smart-b8966262-e6c6-4e1a-a2a4-f84ead7dfc4a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174521396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac
_shadow_reg_errors_with_csr_rw.3174521396 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_errors.2183151844
Short name T1113
Test name
Test status
Simulation time 66215242 ps
CPU time 1.96 seconds
Started Mar 24 12:36:40 PM PDT 24
Finished Mar 24 12:36:45 PM PDT 24
Peak memory 216132 kb
Host smart-8221ebcf-8abc-4ba8-a1ca-1cbfadc825c0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183151844 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.2183151844 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.kmac_tl_intg_err.3471967098
Short name T1153
Test name
Test status
Simulation time 452892573 ps
CPU time 3.86 seconds
Started Mar 24 12:36:29 PM PDT 24
Finished Mar 24 12:36:34 PM PDT 24
Peak memory 216136 kb
Host smart-10dbf5bc-686a-462c-a467-b7f5f1146c41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471967098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.34719
67098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_mem_rw_with_rand_reset.2528131443
Short name T1142
Test name
Test status
Simulation time 70339842 ps
CPU time 2.31 seconds
Started Mar 24 12:36:30 PM PDT 24
Finished Mar 24 12:36:33 PM PDT 24
Peak memory 221884 kb
Host smart-4b5ebd2c-f8f8-4945-9b3f-c20276868adc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528131443 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 8.kmac_csr_mem_rw_with_rand_reset.2528131443 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_csr_rw.1792647095
Short name T1133
Test name
Test status
Simulation time 26358089 ps
CPU time 0.93 seconds
Started Mar 24 12:36:41 PM PDT 24
Finished Mar 24 12:36:44 PM PDT 24
Peak memory 215788 kb
Host smart-88967314-5a40-480c-a4ba-a1bfaa7f4c7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792647095 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_csr_rw.1792647095 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_intr_test.544541951
Short name T1200
Test name
Test status
Simulation time 25268450 ps
CPU time 0.78 seconds
Started Mar 24 12:36:28 PM PDT 24
Finished Mar 24 12:36:31 PM PDT 24
Peak memory 215896 kb
Host smart-b5b57cb2-a901-4c7b-a884-60bab7bf5148
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544541951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.544541951 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/8.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_same_csr_outstanding.1957776668
Short name T1093
Test name
Test status
Simulation time 115214461 ps
CPU time 2.07 seconds
Started Mar 24 12:36:25 PM PDT 24
Finished Mar 24 12:36:27 PM PDT 24
Peak memory 216536 kb
Host smart-c754427a-5857-458f-a199-b66e63203e09
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957776668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_same_csr
_outstanding.1957776668 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors.436316793
Short name T1183
Test name
Test status
Simulation time 25783603 ps
CPU time 1.17 seconds
Started Mar 24 12:36:22 PM PDT 24
Finished Mar 24 12:36:31 PM PDT 24
Peak memory 217496 kb
Host smart-86f3c697-7917-4fae-8b1f-69f3861cba87
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436316793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_e
rrors.436316793 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_shadow_reg_errors_with_csr_rw.3705659943
Short name T1137
Test name
Test status
Simulation time 55915628 ps
CPU time 1.75 seconds
Started Mar 24 12:36:32 PM PDT 24
Finished Mar 24 12:36:35 PM PDT 24
Peak memory 218044 kb
Host smart-e1f67743-941f-4ecb-9f15-5606c5a8f15e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705659943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac
_shadow_reg_errors_with_csr_rw.3705659943 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_errors.3342997440
Short name T152
Test name
Test status
Simulation time 152700665 ps
CPU time 3.52 seconds
Started Mar 24 12:36:24 PM PDT 24
Finished Mar 24 12:36:28 PM PDT 24
Peak memory 216252 kb
Host smart-cc2287d6-7e3d-438b-9aef-9888b362e257
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342997440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.3342997440 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.kmac_tl_intg_err.3938927682
Short name T1128
Test name
Test status
Simulation time 137851594 ps
CPU time 2.92 seconds
Started Mar 24 12:36:18 PM PDT 24
Finished Mar 24 12:36:21 PM PDT 24
Peak memory 216144 kb
Host smart-8c90e89e-a028-49be-a2ad-f0b36d662a8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938927682 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.39389
27682 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_mem_rw_with_rand_reset.2010568462
Short name T1182
Test name
Test status
Simulation time 133778390 ps
CPU time 2.37 seconds
Started Mar 24 12:36:24 PM PDT 24
Finished Mar 24 12:36:27 PM PDT 24
Peak memory 222120 kb
Host smart-01dd029d-5e63-4ffb-9e20-983689b359da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010568462 -assert nopostproc +UVM_TESTNAME
=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 9.kmac_csr_mem_rw_with_rand_reset.2010568462 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_csr_rw.2244084346
Short name T1202
Test name
Test status
Simulation time 22955627 ps
CPU time 0.97 seconds
Started Mar 24 12:36:15 PM PDT 24
Finished Mar 24 12:36:17 PM PDT 24
Peak memory 215952 kb
Host smart-74220e31-fabe-4730-935d-4b96db7cf8d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2244084346 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_csr_rw.2244084346 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_intr_test.1618105511
Short name T1160
Test name
Test status
Simulation time 104006460 ps
CPU time 0.79 seconds
Started Mar 24 12:36:37 PM PDT 24
Finished Mar 24 12:36:44 PM PDT 24
Peak memory 215880 kb
Host smart-d17df5a0-ad80-4cc6-a552-420eecd11848
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618105511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.1618105511 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_same_csr_outstanding.3166939602
Short name T137
Test name
Test status
Simulation time 244434998 ps
CPU time 1.69 seconds
Started Mar 24 12:36:28 PM PDT 24
Finished Mar 24 12:36:32 PM PDT 24
Peak memory 216140 kb
Host smart-0aea649d-9a3c-492e-802e-5b2a74b25f4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166939602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_same_csr
_outstanding.3166939602 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors.3366104083
Short name T1238
Test name
Test status
Simulation time 45376207 ps
CPU time 0.94 seconds
Started Mar 24 12:36:26 PM PDT 24
Finished Mar 24 12:36:28 PM PDT 24
Peak memory 216248 kb
Host smart-41acc6aa-bc6a-4a38-a0dd-ecce76a28936
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366104083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_com
mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_
errors.3366104083 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_shadow_reg_errors_with_csr_rw.2999523956
Short name T1165
Test name
Test status
Simulation time 387474598 ps
CPU time 1.57 seconds
Started Mar 24 12:36:45 PM PDT 24
Finished Mar 24 12:36:47 PM PDT 24
Peak memory 218912 kb
Host smart-826ff161-f5b4-4a8e-9652-96c565a84d77
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999523956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_
SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac
_shadow_reg_errors_with_csr_rw.2999523956 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_errors.621063178
Short name T154
Test name
Test status
Simulation time 372319919 ps
CPU time 2.96 seconds
Started Mar 24 12:36:21 PM PDT 24
Finished Mar 24 12:36:25 PM PDT 24
Peak memory 216192 kb
Host smart-7bf65a63-0637-441b-9dfa-435cc9de6386
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621063178 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.621063178 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.kmac_tl_intg_err.3499037714
Short name T1162
Test name
Test status
Simulation time 142620285 ps
CPU time 3 seconds
Started Mar 24 12:36:17 PM PDT 24
Finished Mar 24 12:36:21 PM PDT 24
Peak memory 216160 kb
Host smart-899bbde0-90d6-41d1-9c14-1653041ed671
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499037714 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.34990
37714 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_tl_intg_err/latest

Test location /workspace/coverage/default/0.kmac_app.2549714838
Short name T339
Test name
Test status
Simulation time 754336919 ps
CPU time 19.1 seconds
Started Mar 24 01:57:44 PM PDT 24
Finished Mar 24 01:58:04 PM PDT 24
Peak memory 224312 kb
Host smart-a8df1433-6fd8-445e-bcf3-12aafc1dae1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2549714838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.2549714838 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app/latest

Test location /workspace/coverage/default/0.kmac_app_with_partial_data.3931154545
Short name T939
Test name
Test status
Simulation time 7052985553 ps
CPU time 259.92 seconds
Started Mar 24 01:57:33 PM PDT 24
Finished Mar 24 02:01:53 PM PDT 24
Peak memory 246196 kb
Host smart-79810ddf-c65d-4939-b168-4fca14f4dbe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931154545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.3931154545 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/0.kmac_burst_write.1027293361
Short name T428
Test name
Test status
Simulation time 68088405439 ps
CPU time 807.95 seconds
Started Mar 24 01:57:28 PM PDT 24
Finished Mar 24 02:10:56 PM PDT 24
Peak memory 237060 kb
Host smart-1600a36b-c39d-4790-8021-f45b4ed0a9e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027293361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.1027293361 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_burst_write/latest

Test location /workspace/coverage/default/0.kmac_edn_timeout_error.3118222602
Short name T801
Test name
Test status
Simulation time 1798333870 ps
CPU time 32.08 seconds
Started Mar 24 01:57:44 PM PDT 24
Finished Mar 24 01:58:17 PM PDT 24
Peak memory 224548 kb
Host smart-204e2f4a-302d-4083-bd2d-34e248338c7d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3118222602 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.3118222602 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_mode_error.1837468374
Short name T146
Test name
Test status
Simulation time 150047486 ps
CPU time 4 seconds
Started Mar 24 01:57:33 PM PDT 24
Finished Mar 24 01:57:37 PM PDT 24
Peak memory 226560 kb
Host smart-6f97ebce-bc3d-4d8b-8ffb-e6931e40012c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1837468374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.1837468374 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_ready_error.982479914
Short name T1022
Test name
Test status
Simulation time 3840883340 ps
CPU time 43.15 seconds
Started Mar 24 01:57:38 PM PDT 24
Finished Mar 24 01:58:21 PM PDT 24
Peak memory 226764 kb
Host smart-32c4fcc4-4d5b-4321-b2bd-3e4cd3fec9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982479914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.982479914 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/0.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/0.kmac_entropy_refresh.3408593027
Short name T857
Test name
Test status
Simulation time 50147520971 ps
CPU time 368.44 seconds
Started Mar 24 01:57:33 PM PDT 24
Finished Mar 24 02:03:42 PM PDT 24
Peak memory 251748 kb
Host smart-fae079fc-0da3-4b79-aea0-4e39442e76ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408593027 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.3408593027 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/0.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/0.kmac_error.2084225386
Short name T474
Test name
Test status
Simulation time 36524525986 ps
CPU time 254.15 seconds
Started Mar 24 01:57:35 PM PDT 24
Finished Mar 24 02:01:49 PM PDT 24
Peak memory 259572 kb
Host smart-6090556d-17de-4dd8-aaac-1a467ec06c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084225386 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.2084225386 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_error/latest

Test location /workspace/coverage/default/0.kmac_key_error.3946894188
Short name T317
Test name
Test status
Simulation time 15187161165 ps
CPU time 6.96 seconds
Started Mar 24 01:57:33 PM PDT 24
Finished Mar 24 01:57:41 PM PDT 24
Peak memory 218572 kb
Host smart-3cebf0c9-3d81-4d1b-92f3-d615017df6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946894188 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3946894188 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_key_error/latest

Test location /workspace/coverage/default/0.kmac_lc_escalation.2280688133
Short name T811
Test name
Test status
Simulation time 74582040 ps
CPU time 1.44 seconds
Started Mar 24 01:57:31 PM PDT 24
Finished Mar 24 01:57:33 PM PDT 24
Peak memory 218588 kb
Host smart-148be06c-a1c2-44cb-8cda-985cccbe6432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280688133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.2280688133 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/0.kmac_lc_escalation/latest

Test location /workspace/coverage/default/0.kmac_long_msg_and_output.24872859
Short name T825
Test name
Test status
Simulation time 104811046874 ps
CPU time 2611.02 seconds
Started Mar 24 01:57:33 PM PDT 24
Finished Mar 24 02:41:05 PM PDT 24
Peak memory 424016 kb
Host smart-bea4e4b6-8845-4aec-ae87-d7649f49902b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24872859 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_
output.24872859 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/0.kmac_mubi.4265571705
Short name T38
Test name
Test status
Simulation time 14820067420 ps
CPU time 376.64 seconds
Started Mar 24 01:57:36 PM PDT 24
Finished Mar 24 02:03:53 PM PDT 24
Peak memory 253384 kb
Host smart-e7447305-5278-40c9-8bf4-75c07907bf4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265571705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.4265571705 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_mubi/latest

Test location /workspace/coverage/default/0.kmac_sideload.3946086827
Short name T814
Test name
Test status
Simulation time 40198267365 ps
CPU time 434.05 seconds
Started Mar 24 01:57:32 PM PDT 24
Finished Mar 24 02:04:46 PM PDT 24
Peak memory 253640 kb
Host smart-019a7ddc-943d-4f64-bdd9-dea1165cd56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946086827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.3946086827 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_sideload/latest

Test location /workspace/coverage/default/0.kmac_smoke.2574469319
Short name T663
Test name
Test status
Simulation time 2887826399 ps
CPU time 19.48 seconds
Started Mar 24 01:57:29 PM PDT 24
Finished Mar 24 01:57:49 PM PDT 24
Peak memory 226716 kb
Host smart-5d012cc9-9423-48e9-b0ee-f2bf2db787dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574469319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.2574469319 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_smoke/latest

Test location /workspace/coverage/default/0.kmac_stress_all.2415913616
Short name T529
Test name
Test status
Simulation time 40761312041 ps
CPU time 1401.46 seconds
Started Mar 24 01:57:33 PM PDT 24
Finished Mar 24 02:20:55 PM PDT 24
Peak memory 343896 kb
Host smart-3252fc92-974a-4f3d-893e-c40a35194e5f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2415913616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all.2415913616 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_stress_all/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac.1040101438
Short name T218
Test name
Test status
Simulation time 186228144 ps
CPU time 6.25 seconds
Started Mar 24 01:57:36 PM PDT 24
Finished Mar 24 01:57:43 PM PDT 24
Peak memory 218640 kb
Host smart-1b1972c5-5f23-44d8-be86-0f184c26e802
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040101438 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 0.kmac_test_vectors_kmac.1040101438 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_kmac_xof.382311174
Short name T848
Test name
Test status
Simulation time 224998489 ps
CPU time 5.54 seconds
Started Mar 24 01:57:33 PM PDT 24
Finished Mar 24 01:57:38 PM PDT 24
Peak memory 226660 kb
Host smart-8446f327-4b6c-407c-a4fc-854714ecb6d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382311174 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 0.kmac_test_vectors_kmac_xof.382311174 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_224.3001338454
Short name T273
Test name
Test status
Simulation time 20267102254 ps
CPU time 1895.18 seconds
Started Mar 24 01:57:31 PM PDT 24
Finished Mar 24 02:29:07 PM PDT 24
Peak memory 397980 kb
Host smart-744f6b1f-30c9-4785-a501-e3222040c513
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3001338454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.3001338454 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_256.2794962392
Short name T179
Test name
Test status
Simulation time 161104690654 ps
CPU time 2231.21 seconds
Started Mar 24 01:57:32 PM PDT 24
Finished Mar 24 02:34:44 PM PDT 24
Peak memory 382508 kb
Host smart-6382444c-0dd4-40e0-8b56-e4deb66c4a5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2794962392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.2794962392 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_384.4033288979
Short name T241
Test name
Test status
Simulation time 16024425573 ps
CPU time 1692.9 seconds
Started Mar 24 01:57:31 PM PDT 24
Finished Mar 24 02:25:45 PM PDT 24
Peak memory 336100 kb
Host smart-0afc1c30-1793-4cf3-aa6d-c23d63064d7f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4033288979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.4033288979 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_sha3_512.2109622343
Short name T557
Test name
Test status
Simulation time 89470163815 ps
CPU time 1245.24 seconds
Started Mar 24 01:57:33 PM PDT 24
Finished Mar 24 02:18:18 PM PDT 24
Peak memory 300500 kb
Host smart-b1602cfe-67b9-48ee-b1d2-5d97a37b131e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2109622343 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.2109622343 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_128.2134218046
Short name T230
Test name
Test status
Simulation time 66152874954 ps
CPU time 5075.25 seconds
Started Mar 24 01:57:36 PM PDT 24
Finished Mar 24 03:22:12 PM PDT 24
Peak memory 657972 kb
Host smart-1e5800e7-f7f9-4ebf-92d0-6a15237b8cd1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2134218046 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.2134218046 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/0.kmac_test_vectors_shake_256.666207458
Short name T594
Test name
Test status
Simulation time 153649638473 ps
CPU time 4628.36 seconds
Started Mar 24 01:57:44 PM PDT 24
Finished Mar 24 03:14:53 PM PDT 24
Peak memory 573856 kb
Host smart-da85f3c1-bea2-40e2-ac6e-58f0ed148733
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=666207458 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.666207458 +enable_masking=1 +sw_key_masked=0
Directory /workspace/0.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/1.kmac_alert_test.1279796925
Short name T816
Test name
Test status
Simulation time 43352462 ps
CPU time 0.81 seconds
Started Mar 24 01:57:44 PM PDT 24
Finished Mar 24 01:57:45 PM PDT 24
Peak memory 218500 kb
Host smart-51b416eb-20d1-4e7c-8cf7-f9c7000bcd94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279796925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.1279796925 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_alert_test/latest

Test location /workspace/coverage/default/1.kmac_app.779004248
Short name T466
Test name
Test status
Simulation time 737815973 ps
CPU time 46.27 seconds
Started Mar 24 01:57:39 PM PDT 24
Finished Mar 24 01:58:25 PM PDT 24
Peak memory 226700 kb
Host smart-1012527b-9c25-46ed-928e-85c5647ae681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779004248 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.779004248 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app/latest

Test location /workspace/coverage/default/1.kmac_app_with_partial_data.1853809210
Short name T236
Test name
Test status
Simulation time 25203242504 ps
CPU time 326.24 seconds
Started Mar 24 01:57:38 PM PDT 24
Finished Mar 24 02:03:04 PM PDT 24
Peak memory 249704 kb
Host smart-62c680ab-1192-47ef-bbf0-c0a814c702e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853809210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.1853809210 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/1.kmac_burst_write.1860839106
Short name T795
Test name
Test status
Simulation time 48137351568 ps
CPU time 1078.16 seconds
Started Mar 24 01:57:36 PM PDT 24
Finished Mar 24 02:15:35 PM PDT 24
Peak memory 236980 kb
Host smart-1ea0736a-75ae-471d-9800-a9786918ab31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860839106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.1860839106 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_burst_write/latest

Test location /workspace/coverage/default/1.kmac_edn_timeout_error.726498116
Short name T490
Test name
Test status
Simulation time 1693600935 ps
CPU time 40.56 seconds
Started Mar 24 01:57:39 PM PDT 24
Finished Mar 24 01:58:20 PM PDT 24
Peak memory 236244 kb
Host smart-e60d9f72-8859-4308-bc14-71feb23bbeb1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=726498116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.726498116 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_ready_error.2930850830
Short name T53
Test name
Test status
Simulation time 7416068897 ps
CPU time 25.9 seconds
Started Mar 24 01:57:38 PM PDT 24
Finished Mar 24 01:58:04 PM PDT 24
Peak memory 226780 kb
Host smart-1d1c7395-d4f0-4cb9-87d1-44d0b824d633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930850830 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.2930850830 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/1.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/1.kmac_entropy_refresh.3146243669
Short name T974
Test name
Test status
Simulation time 8884759895 ps
CPU time 222.18 seconds
Started Mar 24 01:57:37 PM PDT 24
Finished Mar 24 02:01:19 PM PDT 24
Peak memory 243232 kb
Host smart-77f72648-9d4f-4319-9a68-85c33512ed43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146243669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.3146243669 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/1.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/1.kmac_error.719759540
Short name T57
Test name
Test status
Simulation time 13592713836 ps
CPU time 367.98 seconds
Started Mar 24 01:57:37 PM PDT 24
Finished Mar 24 02:03:46 PM PDT 24
Peak memory 267764 kb
Host smart-929a774f-b9ef-4e5b-b605-c600e756cc27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719759540 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.719759540 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_error/latest

Test location /workspace/coverage/default/1.kmac_key_error.1006564328
Short name T418
Test name
Test status
Simulation time 2148353023 ps
CPU time 6.18 seconds
Started Mar 24 01:57:38 PM PDT 24
Finished Mar 24 01:57:45 PM PDT 24
Peak memory 218580 kb
Host smart-61d3f961-01e7-4e51-a9cf-d961902756b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006564328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.1006564328 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_key_error/latest

Test location /workspace/coverage/default/1.kmac_lc_escalation.1073914252
Short name T21
Test name
Test status
Simulation time 75264965 ps
CPU time 1.4 seconds
Started Mar 24 01:57:40 PM PDT 24
Finished Mar 24 01:57:41 PM PDT 24
Peak memory 218668 kb
Host smart-4a263d52-b2e4-4986-859b-ff81e3dbafbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073914252 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.1073914252 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/1.kmac_lc_escalation/latest

Test location /workspace/coverage/default/1.kmac_long_msg_and_output.1554601013
Short name T123
Test name
Test status
Simulation time 1915224308 ps
CPU time 45.69 seconds
Started Mar 24 01:57:36 PM PDT 24
Finished Mar 24 01:58:22 PM PDT 24
Peak memory 225856 kb
Host smart-b01f9af5-20a8-4be2-ae3d-feac40d4ab4c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554601013 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_an
d_output.1554601013 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/1.kmac_mubi.2146429641
Short name T959
Test name
Test status
Simulation time 1536938702 ps
CPU time 103.25 seconds
Started Mar 24 01:57:47 PM PDT 24
Finished Mar 24 01:59:30 PM PDT 24
Peak memory 233796 kb
Host smart-041f404b-2bf6-4476-8d90-449e265b87de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146429641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.2146429641 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_mubi/latest

Test location /workspace/coverage/default/1.kmac_sideload.264370774
Short name T407
Test name
Test status
Simulation time 19367927394 ps
CPU time 331.18 seconds
Started Mar 24 01:57:38 PM PDT 24
Finished Mar 24 02:03:09 PM PDT 24
Peak memory 246380 kb
Host smart-a5c4bd78-d8e1-4a18-99b2-c7896d952f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264370774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.264370774 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_sideload/latest

Test location /workspace/coverage/default/1.kmac_smoke.2835976318
Short name T142
Test name
Test status
Simulation time 1156497282 ps
CPU time 41.97 seconds
Started Mar 24 01:57:42 PM PDT 24
Finished Mar 24 01:58:24 PM PDT 24
Peak memory 223104 kb
Host smart-bee37b43-c5b0-4fd2-9a9c-18f2bd5d7a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835976318 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.2835976318 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_smoke/latest

Test location /workspace/coverage/default/1.kmac_stress_all.2261951333
Short name T243
Test name
Test status
Simulation time 390610702000 ps
CPU time 850.02 seconds
Started Mar 24 01:57:37 PM PDT 24
Finished Mar 24 02:11:47 PM PDT 24
Peak memory 295416 kb
Host smart-e1c9fe79-bd2e-4faa-9929-6e5580403a5e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2261951333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all.2261951333 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_stress_all/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac.2557368491
Short name T792
Test name
Test status
Simulation time 985384326 ps
CPU time 5.8 seconds
Started Mar 24 01:57:39 PM PDT 24
Finished Mar 24 01:57:45 PM PDT 24
Peak memory 218700 kb
Host smart-e408edaa-e66f-4987-8de0-24b37013d301
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557368491 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 1.kmac_test_vectors_kmac.2557368491 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_kmac_xof.3796165790
Short name T1033
Test name
Test status
Simulation time 464760708 ps
CPU time 5.69 seconds
Started Mar 24 01:57:36 PM PDT 24
Finished Mar 24 01:57:42 PM PDT 24
Peak memory 226676 kb
Host smart-655a2d80-dee4-4957-b47f-2ecf927f91d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796165790 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3796165790 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_224.3544655434
Short name T837
Test name
Test status
Simulation time 278541581333 ps
CPU time 2289.1 seconds
Started Mar 24 01:57:47 PM PDT 24
Finished Mar 24 02:35:57 PM PDT 24
Peak memory 405572 kb
Host smart-d606e43e-96c5-4c81-8b09-3a1755173780
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3544655434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.3544655434 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_256.4274830365
Short name T192
Test name
Test status
Simulation time 85736039069 ps
CPU time 1781.2 seconds
Started Mar 24 01:57:47 PM PDT 24
Finished Mar 24 02:27:29 PM PDT 24
Peak memory 384808 kb
Host smart-f384be0a-6832-48a1-963e-eb8c197b55a1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4274830365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.4274830365 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_384.2854001783
Short name T643
Test name
Test status
Simulation time 15674056814 ps
CPU time 1547.12 seconds
Started Mar 24 01:57:47 PM PDT 24
Finished Mar 24 02:23:35 PM PDT 24
Peak memory 341048 kb
Host smart-48deefaa-e05a-454c-9921-0ecdeb0bdcfa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2854001783 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.2854001783 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_sha3_512.226456330
Short name T1025
Test name
Test status
Simulation time 10389473673 ps
CPU time 1344.42 seconds
Started Mar 24 01:57:36 PM PDT 24
Finished Mar 24 02:20:01 PM PDT 24
Peak memory 301456 kb
Host smart-b2edb18f-d247-468f-924e-a906e5202170
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=226456330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.226456330 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_128.1316247658
Short name T556
Test name
Test status
Simulation time 743903180222 ps
CPU time 6043.77 seconds
Started Mar 24 01:57:36 PM PDT 24
Finished Mar 24 03:38:21 PM PDT 24
Peak memory 662656 kb
Host smart-7456ddff-4fed-4280-8cac-1c582291f860
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1316247658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1316247658 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/1.kmac_test_vectors_shake_256.2619703831
Short name T805
Test name
Test status
Simulation time 529591801291 ps
CPU time 4929.85 seconds
Started Mar 24 01:57:40 PM PDT 24
Finished Mar 24 03:19:51 PM PDT 24
Peak memory 563932 kb
Host smart-fd7cea47-18cf-4f3d-8ac4-79bbf34a4cf2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2619703831 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.2619703831 +enable_masking=1 +sw_key_masked=0
Directory /workspace/1.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/10.kmac_alert_test.2099992043
Short name T1007
Test name
Test status
Simulation time 62580189 ps
CPU time 0.81 seconds
Started Mar 24 01:58:38 PM PDT 24
Finished Mar 24 01:58:39 PM PDT 24
Peak memory 218532 kb
Host smart-c7ff85b0-7261-480b-9919-063ed69efad6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099992043 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_alert_test.2099992043 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_alert_test/latest

Test location /workspace/coverage/default/10.kmac_app.816685710
Short name T535
Test name
Test status
Simulation time 6608676161 ps
CPU time 172.5 seconds
Started Mar 24 01:58:39 PM PDT 24
Finished Mar 24 02:01:32 PM PDT 24
Peak memory 240224 kb
Host smart-d1c9f7e0-9369-4812-98f1-54d5bce985ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816685710 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.816685710 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_app/latest

Test location /workspace/coverage/default/10.kmac_burst_write.3958893799
Short name T958
Test name
Test status
Simulation time 14695936094 ps
CPU time 1380 seconds
Started Mar 24 01:58:32 PM PDT 24
Finished Mar 24 02:21:33 PM PDT 24
Peak memory 238536 kb
Host smart-50846fd1-be75-41f9-a0b4-d01ba2e9ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958893799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.3958893799 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_burst_write/latest

Test location /workspace/coverage/default/10.kmac_edn_timeout_error.1898893473
Short name T103
Test name
Test status
Simulation time 936604338 ps
CPU time 5.76 seconds
Started Mar 24 01:58:38 PM PDT 24
Finished Mar 24 01:58:44 PM PDT 24
Peak memory 219536 kb
Host smart-d2e2a658-f6bd-4dd1-8beb-8a9dbfe06804
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1898893473 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.1898893473 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_mode_error.4072490638
Short name T506
Test name
Test status
Simulation time 6954827995 ps
CPU time 51.72 seconds
Started Mar 24 01:58:36 PM PDT 24
Finished Mar 24 01:59:28 PM PDT 24
Peak memory 227832 kb
Host smart-fa4b6874-11b2-4f64-9d1c-c4cbe9e7e2cc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4072490638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.4072490638 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/10.kmac_entropy_refresh.796343311
Short name T973
Test name
Test status
Simulation time 55740276924 ps
CPU time 390.97 seconds
Started Mar 24 01:58:36 PM PDT 24
Finished Mar 24 02:05:08 PM PDT 24
Peak memory 253176 kb
Host smart-b23ba748-e943-4192-b71e-17629d311001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796343311 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.796343311 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/10.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/10.kmac_error.2533944933
Short name T48
Test name
Test status
Simulation time 12699091721 ps
CPU time 235.2 seconds
Started Mar 24 01:58:37 PM PDT 24
Finished Mar 24 02:02:32 PM PDT 24
Peak memory 259476 kb
Host smart-76eaa09a-c537-459c-9302-6d2e562d8ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533944933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.2533944933 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_error/latest

Test location /workspace/coverage/default/10.kmac_key_error.4145855936
Short name T665
Test name
Test status
Simulation time 1004109546 ps
CPU time 5.51 seconds
Started Mar 24 01:58:37 PM PDT 24
Finished Mar 24 01:58:42 PM PDT 24
Peak memory 218552 kb
Host smart-33ee2194-7be0-4811-a4f6-f2b3f4541af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145855936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.4145855936 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_key_error/latest

Test location /workspace/coverage/default/10.kmac_long_msg_and_output.651087331
Short name T80
Test name
Test status
Simulation time 360736188216 ps
CPU time 1944.58 seconds
Started Mar 24 01:58:32 PM PDT 24
Finished Mar 24 02:30:57 PM PDT 24
Peak memory 363620 kb
Host smart-9ed49422-3eb5-4e89-84aa-ba1ebfe69d89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651087331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_an
d_output.651087331 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/10.kmac_sideload.2545689223
Short name T678
Test name
Test status
Simulation time 16971338100 ps
CPU time 92.45 seconds
Started Mar 24 01:58:34 PM PDT 24
Finished Mar 24 02:00:07 PM PDT 24
Peak memory 231156 kb
Host smart-3742f087-9b5f-4509-abcd-34fd9a02ca46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545689223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2545689223 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_sideload/latest

Test location /workspace/coverage/default/10.kmac_smoke.3448306117
Short name T205
Test name
Test status
Simulation time 2557109808 ps
CPU time 46.51 seconds
Started Mar 24 01:58:32 PM PDT 24
Finished Mar 24 01:59:19 PM PDT 24
Peak memory 226768 kb
Host smart-baa492e6-ad85-47ad-9a48-d131b4d37566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448306117 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.3448306117 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_smoke/latest

Test location /workspace/coverage/default/10.kmac_stress_all.766758380
Short name T708
Test name
Test status
Simulation time 33742929497 ps
CPU time 1438.74 seconds
Started Mar 24 01:58:37 PM PDT 24
Finished Mar 24 02:22:36 PM PDT 24
Peak memory 333512 kb
Host smart-ffd72ecd-a7c4-45e2-a155-1ffa9c6eed36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=766758380 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_stress_all.766758380 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_stress_all/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac.3878364319
Short name T316
Test name
Test status
Simulation time 732164905 ps
CPU time 6.02 seconds
Started Mar 24 01:58:37 PM PDT 24
Finished Mar 24 01:58:43 PM PDT 24
Peak memory 226680 kb
Host smart-8359067e-1825-488c-8409-36ef3e0bf355
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878364319 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 10.kmac_test_vectors_kmac.3878364319 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_kmac_xof.3693671521
Short name T883
Test name
Test status
Simulation time 250620050 ps
CPU time 6.28 seconds
Started Mar 24 01:58:37 PM PDT 24
Finished Mar 24 01:58:44 PM PDT 24
Peak memory 218620 kb
Host smart-7b91d7b9-8623-4a59-aa7a-49e4ddd8a675
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693671521 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 10.kmac_test_vectors_kmac_xof.3693671521 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_224.3116744727
Short name T764
Test name
Test status
Simulation time 337386438962 ps
CPU time 2281.64 seconds
Started Mar 24 01:58:32 PM PDT 24
Finished Mar 24 02:36:34 PM PDT 24
Peak memory 396216 kb
Host smart-31b68287-b7d1-493f-a444-47857d2a9cc3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3116744727 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_224.3116744727 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_256.1872368423
Short name T910
Test name
Test status
Simulation time 65175772552 ps
CPU time 1819.28 seconds
Started Mar 24 01:58:33 PM PDT 24
Finished Mar 24 02:28:52 PM PDT 24
Peak memory 381004 kb
Host smart-04bbc9c2-4870-4877-969e-f6b6f0bf9642
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1872368423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_256.1872368423 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_384.2964004966
Short name T354
Test name
Test status
Simulation time 123496780738 ps
CPU time 1709.41 seconds
Started Mar 24 01:58:33 PM PDT 24
Finished Mar 24 02:27:03 PM PDT 24
Peak memory 337972 kb
Host smart-db381843-0e05-42b3-ba0c-2876ecbfd8a0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2964004966 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_384.2964004966 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_sha3_512.3695960564
Short name T969
Test name
Test status
Simulation time 50984969632 ps
CPU time 1251.23 seconds
Started Mar 24 01:58:36 PM PDT 24
Finished Mar 24 02:19:28 PM PDT 24
Peak memory 298168 kb
Host smart-87871245-4f75-4420-b076-e9a5c6b1e6ed
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3695960564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_sha3_512.3695960564 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_128.2902610381
Short name T452
Test name
Test status
Simulation time 451023642576 ps
CPU time 5943.13 seconds
Started Mar 24 01:58:36 PM PDT 24
Finished Mar 24 03:37:41 PM PDT 24
Peak memory 647660 kb
Host smart-7841f701-719e-4124-ad31-4b01b9e43de0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2902610381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_128.2902610381 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/10.kmac_test_vectors_shake_256.1449835645
Short name T918
Test name
Test status
Simulation time 620192387238 ps
CPU time 4856.34 seconds
Started Mar 24 01:58:38 PM PDT 24
Finished Mar 24 03:19:35 PM PDT 24
Peak memory 569660 kb
Host smart-be542e48-86a5-4ff5-a83c-157cd5b40df7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1449835645 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_test_vectors_shake_256.1449835645 +enable_masking=1 +sw_key_masked=0
Directory /workspace/10.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/11.kmac_alert_test.1307756479
Short name T368
Test name
Test status
Simulation time 34045796 ps
CPU time 0.82 seconds
Started Mar 24 01:58:55 PM PDT 24
Finished Mar 24 01:58:56 PM PDT 24
Peak memory 218444 kb
Host smart-890214e1-f993-4384-96d8-3026daf76ca4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307756479 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_alert_test.1307756479 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_alert_test/latest

Test location /workspace/coverage/default/11.kmac_app.3984044102
Short name T299
Test name
Test status
Simulation time 2503252566 ps
CPU time 148.52 seconds
Started Mar 24 01:58:51 PM PDT 24
Finished Mar 24 02:01:20 PM PDT 24
Peak memory 236544 kb
Host smart-114ce062-dbc2-4369-8bda-d6446582c14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984044102 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.3984044102 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_app/latest

Test location /workspace/coverage/default/11.kmac_burst_write.996498112
Short name T639
Test name
Test status
Simulation time 89018130250 ps
CPU time 1389.07 seconds
Started Mar 24 01:58:41 PM PDT 24
Finished Mar 24 02:21:51 PM PDT 24
Peak memory 243164 kb
Host smart-0a0389ed-3d11-4ed3-a74a-45d8207787f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996498112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.996498112 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_burst_write/latest

Test location /workspace/coverage/default/11.kmac_entropy_mode_error.1987160711
Short name T995
Test name
Test status
Simulation time 2246507080 ps
CPU time 45.26 seconds
Started Mar 24 01:58:50 PM PDT 24
Finished Mar 24 01:59:36 PM PDT 24
Peak memory 226892 kb
Host smart-3683da66-22b6-4367-abd8-7eb37e9d543a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1987160711 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.1987160711 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/11.kmac_entropy_refresh.3602631044
Short name T430
Test name
Test status
Simulation time 34360624006 ps
CPU time 210.54 seconds
Started Mar 24 01:58:50 PM PDT 24
Finished Mar 24 02:02:20 PM PDT 24
Peak memory 242724 kb
Host smart-8b39a1ee-f740-472c-bad7-4d2ffb8622e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602631044 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.3602631044 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/11.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/11.kmac_error.1137923278
Short name T769
Test name
Test status
Simulation time 903825674 ps
CPU time 78.73 seconds
Started Mar 24 01:58:51 PM PDT 24
Finished Mar 24 02:00:10 PM PDT 24
Peak memory 243332 kb
Host smart-8cbf298c-3872-43af-8c4b-d5f10be317bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137923278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.1137923278 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_error/latest

Test location /workspace/coverage/default/11.kmac_key_error.2535431699
Short name T288
Test name
Test status
Simulation time 1103548869 ps
CPU time 2.53 seconds
Started Mar 24 01:58:51 PM PDT 24
Finished Mar 24 01:58:54 PM PDT 24
Peak memory 218548 kb
Host smart-81aeecde-b6e2-4648-9486-11fdc3f231ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535431699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.2535431699 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_key_error/latest

Test location /workspace/coverage/default/11.kmac_lc_escalation.327133282
Short name T573
Test name
Test status
Simulation time 59241816 ps
CPU time 1.26 seconds
Started Mar 24 01:58:49 PM PDT 24
Finished Mar 24 01:58:50 PM PDT 24
Peak memory 218596 kb
Host smart-1efb842a-0793-4cbf-9010-2e07563ff017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327133282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.327133282 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/11.kmac_lc_escalation/latest

Test location /workspace/coverage/default/11.kmac_long_msg_and_output.1834478365
Short name T290
Test name
Test status
Simulation time 131019325443 ps
CPU time 1747.28 seconds
Started Mar 24 01:58:41 PM PDT 24
Finished Mar 24 02:27:48 PM PDT 24
Peak memory 347792 kb
Host smart-6e2ab9ce-9d17-461e-a27d-bb81435c76ef
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834478365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_a
nd_output.1834478365 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/11.kmac_sideload.1257657931
Short name T1024
Test name
Test status
Simulation time 4523629414 ps
CPU time 411.84 seconds
Started Mar 24 01:58:42 PM PDT 24
Finished Mar 24 02:05:34 PM PDT 24
Peak memory 253224 kb
Host smart-d0456286-68c5-4ab4-9c1a-34b6c2c15920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257657931 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.1257657931 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_sideload/latest

Test location /workspace/coverage/default/11.kmac_smoke.4123968001
Short name T878
Test name
Test status
Simulation time 3574815796 ps
CPU time 35.38 seconds
Started Mar 24 01:58:42 PM PDT 24
Finished Mar 24 01:59:18 PM PDT 24
Peak memory 226716 kb
Host smart-32fb22ed-6e15-44dc-8efd-ef3980c08acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123968001 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.4123968001 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_smoke/latest

Test location /workspace/coverage/default/11.kmac_stress_all.3021703385
Short name T700
Test name
Test status
Simulation time 8997125720 ps
CPU time 383.38 seconds
Started Mar 24 01:58:51 PM PDT 24
Finished Mar 24 02:05:15 PM PDT 24
Peak memory 257512 kb
Host smart-3466dbb2-69f3-464c-8de0-508143d7241d
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3021703385 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_stress_all.3021703385 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_stress_all/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac.3235058306
Short name T1058
Test name
Test status
Simulation time 183563510 ps
CPU time 6.77 seconds
Started Mar 24 01:58:47 PM PDT 24
Finished Mar 24 01:58:54 PM PDT 24
Peak memory 218884 kb
Host smart-08a686c3-5d6c-46ef-a0d3-b6eefdc8b0c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235058306 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 11.kmac_test_vectors_kmac.3235058306 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_kmac_xof.4021238573
Short name T672
Test name
Test status
Simulation time 248205719 ps
CPU time 6.35 seconds
Started Mar 24 01:58:50 PM PDT 24
Finished Mar 24 01:58:57 PM PDT 24
Peak memory 218644 kb
Host smart-8e831f4c-378f-4abe-a021-64d61ee1248c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021238573 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 11.kmac_test_vectors_kmac_xof.4021238573 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_224.2352313850
Short name T874
Test name
Test status
Simulation time 29174359219 ps
CPU time 2196 seconds
Started Mar 24 01:58:43 PM PDT 24
Finished Mar 24 02:35:19 PM PDT 24
Peak memory 396288 kb
Host smart-a5e1f446-bbd6-454e-be65-6213a2117f2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2352313850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_224.2352313850 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_256.1736199085
Short name T570
Test name
Test status
Simulation time 63815607960 ps
CPU time 2163.12 seconds
Started Mar 24 01:58:42 PM PDT 24
Finished Mar 24 02:34:45 PM PDT 24
Peak memory 394788 kb
Host smart-07feebc3-f83d-402a-82f4-8a32a0e4a87b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1736199085 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_256.1736199085 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_384.3085952258
Short name T1005
Test name
Test status
Simulation time 59024653236 ps
CPU time 1620.48 seconds
Started Mar 24 01:58:41 PM PDT 24
Finished Mar 24 02:25:42 PM PDT 24
Peak memory 336796 kb
Host smart-2a827a9b-278d-44f8-a550-c5d05f3aee42
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3085952258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_384.3085952258 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_sha3_512.2410330777
Short name T921
Test name
Test status
Simulation time 44145358448 ps
CPU time 1234.07 seconds
Started Mar 24 01:58:46 PM PDT 24
Finished Mar 24 02:19:20 PM PDT 24
Peak memory 299032 kb
Host smart-f53df860-92f0-41b0-8b6a-8e810f4ecd7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2410330777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_sha3_512.2410330777 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_128.3199051422
Short name T650
Test name
Test status
Simulation time 502815959765 ps
CPU time 6209.03 seconds
Started Mar 24 01:58:45 PM PDT 24
Finished Mar 24 03:42:15 PM PDT 24
Peak memory 645460 kb
Host smart-c3bcce52-edc1-43ac-9e24-e0cfee9d9565
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3199051422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_128.3199051422 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/11.kmac_test_vectors_shake_256.2604408266
Short name T657
Test name
Test status
Simulation time 226439103204 ps
CPU time 4331.58 seconds
Started Mar 24 01:58:46 PM PDT 24
Finished Mar 24 03:10:58 PM PDT 24
Peak memory 568216 kb
Host smart-a7cb3e5b-d6a6-4a53-8f64-df6dfe83b886
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2604408266 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_test_vectors_shake_256.2604408266 +enable_masking=1 +sw_key_masked=0
Directory /workspace/11.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/12.kmac_alert_test.2201151400
Short name T676
Test name
Test status
Simulation time 42918281 ps
CPU time 0.85 seconds
Started Mar 24 01:59:04 PM PDT 24
Finished Mar 24 01:59:05 PM PDT 24
Peak memory 218488 kb
Host smart-68413270-d51f-4768-85dd-d949af9ec846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201151400 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_alert_test.2201151400 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_alert_test/latest

Test location /workspace/coverage/default/12.kmac_app.1609384633
Short name T869
Test name
Test status
Simulation time 5441353166 ps
CPU time 347.9 seconds
Started Mar 24 01:58:59 PM PDT 24
Finished Mar 24 02:04:48 PM PDT 24
Peak memory 251232 kb
Host smart-c8854270-7270-4269-8e43-ca338476722f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609384633 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.1609384633 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_app/latest

Test location /workspace/coverage/default/12.kmac_burst_write.2274931648
Short name T130
Test name
Test status
Simulation time 21647239243 ps
CPU time 196.06 seconds
Started Mar 24 01:58:55 PM PDT 24
Finished Mar 24 02:02:12 PM PDT 24
Peak memory 228620 kb
Host smart-edfd37ab-294a-42c8-bf39-c7f7051db68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274931648 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.2274931648 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_burst_write/latest

Test location /workspace/coverage/default/12.kmac_edn_timeout_error.3305110066
Short name T888
Test name
Test status
Simulation time 883345680 ps
CPU time 5.93 seconds
Started Mar 24 01:59:01 PM PDT 24
Finished Mar 24 01:59:08 PM PDT 24
Peak memory 221932 kb
Host smart-7b8c665a-a3a2-4124-aec5-66930588fe30
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3305110066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.3305110066 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_mode_error.3446874943
Short name T896
Test name
Test status
Simulation time 24823685 ps
CPU time 0.99 seconds
Started Mar 24 01:59:05 PM PDT 24
Finished Mar 24 01:59:06 PM PDT 24
Peak memory 221480 kb
Host smart-2d052b35-246b-48e1-aab1-72bc57efab78
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3446874943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.3446874943 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/12.kmac_entropy_refresh.801327882
Short name T497
Test name
Test status
Simulation time 27799172196 ps
CPU time 409.78 seconds
Started Mar 24 01:58:59 PM PDT 24
Finished Mar 24 02:05:50 PM PDT 24
Peak memory 255292 kb
Host smart-22ce5e25-0651-491f-80ed-7c86e4f8b7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801327882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.801327882 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/12.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/12.kmac_error.2249866329
Short name T1046
Test name
Test status
Simulation time 12739293995 ps
CPU time 149.93 seconds
Started Mar 24 01:59:00 PM PDT 24
Finished Mar 24 02:01:31 PM PDT 24
Peak memory 251384 kb
Host smart-dd29a0d8-9624-4c89-bb7b-fb0a0aa07419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249866329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.2249866329 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_error/latest

Test location /workspace/coverage/default/12.kmac_key_error.751513802
Short name T757
Test name
Test status
Simulation time 3850637435 ps
CPU time 6.67 seconds
Started Mar 24 01:58:59 PM PDT 24
Finished Mar 24 01:59:06 PM PDT 24
Peak memory 218680 kb
Host smart-253279fc-8ae5-46e3-9e16-31d8e357cec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751513802 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.751513802 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_key_error/latest

Test location /workspace/coverage/default/12.kmac_lc_escalation.147346056
Short name T602
Test name
Test status
Simulation time 76327468 ps
CPU time 1.33 seconds
Started Mar 24 01:59:04 PM PDT 24
Finished Mar 24 01:59:06 PM PDT 24
Peak memory 218608 kb
Host smart-9615a719-d93f-47b5-b0d8-da16dc21a2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147346056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.147346056 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/12.kmac_lc_escalation/latest

Test location /workspace/coverage/default/12.kmac_long_msg_and_output.595089771
Short name T664
Test name
Test status
Simulation time 81910042596 ps
CPU time 3091.48 seconds
Started Mar 24 01:58:54 PM PDT 24
Finished Mar 24 02:50:26 PM PDT 24
Peak memory 460988 kb
Host smart-0eae8823-0646-41e1-9bf8-13cb07b94f60
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595089771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_an
d_output.595089771 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/12.kmac_sideload.1221496008
Short name T718
Test name
Test status
Simulation time 35109739090 ps
CPU time 445.19 seconds
Started Mar 24 01:58:55 PM PDT 24
Finished Mar 24 02:06:21 PM PDT 24
Peak memory 253192 kb
Host smart-0ffdebcf-e4b8-4713-bd82-19ee654c28f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221496008 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.1221496008 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_sideload/latest

Test location /workspace/coverage/default/12.kmac_smoke.2823619449
Short name T122
Test name
Test status
Simulation time 3058402995 ps
CPU time 62.61 seconds
Started Mar 24 01:58:55 PM PDT 24
Finished Mar 24 01:59:58 PM PDT 24
Peak memory 221796 kb
Host smart-9d46a247-3b98-401c-afa7-7f673046e8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823619449 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.2823619449 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_smoke/latest

Test location /workspace/coverage/default/12.kmac_stress_all.3097660433
Short name T163
Test name
Test status
Simulation time 10047388179 ps
CPU time 539.25 seconds
Started Mar 24 01:59:04 PM PDT 24
Finished Mar 24 02:08:03 PM PDT 24
Peak memory 300844 kb
Host smart-0fea5dac-81c9-47f7-831e-3c6adcd91d04
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3097660433 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all.3097660433 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all/latest

Test location /workspace/coverage/default/12.kmac_stress_all_with_rand_reset.2593091303
Short name T117
Test name
Test status
Simulation time 42820879787 ps
CPU time 346.1 seconds
Started Mar 24 01:59:04 PM PDT 24
Finished Mar 24 02:04:51 PM PDT 24
Peak memory 267656 kb
Host smart-4c030157-9d3b-41cc-b3c5-1ca850317fde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2593091303 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_stress_all_with_rand_reset.2593091303 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac.3316311939
Short name T329
Test name
Test status
Simulation time 829772008 ps
CPU time 6.37 seconds
Started Mar 24 01:59:00 PM PDT 24
Finished Mar 24 01:59:07 PM PDT 24
Peak memory 226744 kb
Host smart-3ca3398d-dff3-4361-ad7d-2acb2a2563d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316311939 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 12.kmac_test_vectors_kmac.3316311939 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_kmac_xof.1289923530
Short name T352
Test name
Test status
Simulation time 153566844 ps
CPU time 5.95 seconds
Started Mar 24 01:59:01 PM PDT 24
Finished Mar 24 01:59:07 PM PDT 24
Peak memory 218640 kb
Host smart-2979bb12-ba09-4822-abe1-e8bcc79b7b5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289923530 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 12.kmac_test_vectors_kmac_xof.1289923530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_224.1774559205
Short name T191
Test name
Test status
Simulation time 113076220942 ps
CPU time 1953.23 seconds
Started Mar 24 01:58:54 PM PDT 24
Finished Mar 24 02:31:29 PM PDT 24
Peak memory 394320 kb
Host smart-3f478537-f1a3-49ca-93ae-ed30d536806e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1774559205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_224.1774559205 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_256.914678158
Short name T577
Test name
Test status
Simulation time 247528143947 ps
CPU time 2199.65 seconds
Started Mar 24 01:58:55 PM PDT 24
Finished Mar 24 02:35:36 PM PDT 24
Peak memory 385688 kb
Host smart-d399191c-6e10-41a6-809a-92964013d33e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=914678158 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_256.914678158 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_384.446785706
Short name T434
Test name
Test status
Simulation time 199386383034 ps
CPU time 1818.99 seconds
Started Mar 24 01:58:59 PM PDT 24
Finished Mar 24 02:29:19 PM PDT 24
Peak memory 342420 kb
Host smart-8a58d641-c157-49c5-95dd-3d22d3ea72eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=446785706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_384.446785706 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_sha3_512.1216667616
Short name T296
Test name
Test status
Simulation time 20133893016 ps
CPU time 1120.69 seconds
Started Mar 24 01:59:01 PM PDT 24
Finished Mar 24 02:17:42 PM PDT 24
Peak memory 298508 kb
Host smart-f0dbca30-9dcf-49c2-805b-949adf559497
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1216667616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_sha3_512.1216667616 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_128.749962644
Short name T953
Test name
Test status
Simulation time 310261932909 ps
CPU time 5060.77 seconds
Started Mar 24 01:59:01 PM PDT 24
Finished Mar 24 03:23:23 PM PDT 24
Peak memory 638724 kb
Host smart-c8a75d6b-c5dc-4074-96dc-7867b035c90a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=749962644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_128.749962644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/12.kmac_test_vectors_shake_256.1368408282
Short name T591
Test name
Test status
Simulation time 158907109187 ps
CPU time 4941.34 seconds
Started Mar 24 01:59:01 PM PDT 24
Finished Mar 24 03:21:23 PM PDT 24
Peak memory 569600 kb
Host smart-c558928a-43f3-44c9-b3db-80ee6fd98917
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1368408282 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_test_vectors_shake_256.1368408282 +enable_masking=1 +sw_key_masked=0
Directory /workspace/12.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/13.kmac_alert_test.534275944
Short name T578
Test name
Test status
Simulation time 22442378 ps
CPU time 0.77 seconds
Started Mar 24 01:59:18 PM PDT 24
Finished Mar 24 01:59:19 PM PDT 24
Peak memory 218472 kb
Host smart-84ceaab5-1d81-4eaa-a2d1-e9bb80c7bd49
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534275944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_alert_test.534275944 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/13.kmac_alert_test/latest

Test location /workspace/coverage/default/13.kmac_burst_write.4152124309
Short name T777
Test name
Test status
Simulation time 27980331435 ps
CPU time 774.65 seconds
Started Mar 24 01:59:08 PM PDT 24
Finished Mar 24 02:12:03 PM PDT 24
Peak memory 234632 kb
Host smart-6514d75e-070a-46a8-9b5a-0fc89496400a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152124309 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.4152124309 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_burst_write/latest

Test location /workspace/coverage/default/13.kmac_edn_timeout_error.2652129123
Short name T64
Test name
Test status
Simulation time 96091049 ps
CPU time 1.15 seconds
Started Mar 24 01:59:16 PM PDT 24
Finished Mar 24 01:59:18 PM PDT 24
Peak memory 218604 kb
Host smart-8307bc47-c998-4745-ae1d-6f93888a7adf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2652129123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.2652129123 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_mode_error.204132330
Short name T350
Test name
Test status
Simulation time 1617912035 ps
CPU time 28.27 seconds
Started Mar 24 01:59:16 PM PDT 24
Finished Mar 24 01:59:44 PM PDT 24
Peak memory 226812 kb
Host smart-8ed1336c-0c40-4368-8182-b0d1283d9eae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=204132330 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.204132330 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/13.kmac_entropy_refresh.2338923298
Short name T437
Test name
Test status
Simulation time 7105928111 ps
CPU time 358.64 seconds
Started Mar 24 01:59:17 PM PDT 24
Finished Mar 24 02:05:16 PM PDT 24
Peak memory 250780 kb
Host smart-793bad05-4fa6-4f08-a70b-d04f8d8a6bc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338923298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.2338923298 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/13.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/13.kmac_error.2415093934
Short name T628
Test name
Test status
Simulation time 33951991943 ps
CPU time 279.71 seconds
Started Mar 24 01:59:18 PM PDT 24
Finished Mar 24 02:03:58 PM PDT 24
Peak memory 254544 kb
Host smart-3bc23c77-1a37-4991-b2a6-355722c101c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415093934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.2415093934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_error/latest

Test location /workspace/coverage/default/13.kmac_key_error.2820920640
Short name T641
Test name
Test status
Simulation time 2395752533 ps
CPU time 4.02 seconds
Started Mar 24 01:59:17 PM PDT 24
Finished Mar 24 01:59:22 PM PDT 24
Peak memory 222980 kb
Host smart-a310037b-c01e-40d3-ab43-1cb10d357fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820920640 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.2820920640 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_key_error/latest

Test location /workspace/coverage/default/13.kmac_lc_escalation.1658764850
Short name T25
Test name
Test status
Simulation time 175802894 ps
CPU time 1.52 seconds
Started Mar 24 01:59:17 PM PDT 24
Finished Mar 24 01:59:19 PM PDT 24
Peak memory 218592 kb
Host smart-faed35ee-dcca-4451-935b-22850fd1a0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658764850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.1658764850 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/13.kmac_lc_escalation/latest

Test location /workspace/coverage/default/13.kmac_long_msg_and_output.381964699
Short name T378
Test name
Test status
Simulation time 21530533038 ps
CPU time 2139.46 seconds
Started Mar 24 01:59:09 PM PDT 24
Finished Mar 24 02:34:48 PM PDT 24
Peak memory 405700 kb
Host smart-3d8cebc5-dcf3-4e70-8938-972790704a8b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381964699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_an
d_output.381964699 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/13.kmac_sideload.2269282680
Short name T523
Test name
Test status
Simulation time 41547148121 ps
CPU time 504.65 seconds
Started Mar 24 01:59:10 PM PDT 24
Finished Mar 24 02:07:35 PM PDT 24
Peak memory 260108 kb
Host smart-18cabbfe-36ac-475c-9b7a-63636416501b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269282680 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.2269282680 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_sideload/latest

Test location /workspace/coverage/default/13.kmac_smoke.157151271
Short name T586
Test name
Test status
Simulation time 17863660297 ps
CPU time 92.38 seconds
Started Mar 24 01:59:04 PM PDT 24
Finished Mar 24 02:00:37 PM PDT 24
Peak memory 226772 kb
Host smart-2e045bcc-a0cb-4090-8a8e-261ffb7a64c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157151271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.157151271 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_smoke/latest

Test location /workspace/coverage/default/13.kmac_stress_all.98637955
Short name T164
Test name
Test status
Simulation time 103094155396 ps
CPU time 2770.96 seconds
Started Mar 24 01:59:17 PM PDT 24
Finished Mar 24 02:45:29 PM PDT 24
Peak memory 480960 kb
Host smart-5e4a838c-b10b-4fcb-bd02-8809a2d18603
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=98637955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_stress_all.98637955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_stress_all/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac.3581441231
Short name T660
Test name
Test status
Simulation time 195315920 ps
CPU time 6.84 seconds
Started Mar 24 01:59:15 PM PDT 24
Finished Mar 24 01:59:22 PM PDT 24
Peak memory 226732 kb
Host smart-23236974-a225-4bc1-a670-311ad3cdfcc9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581441231 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 13.kmac_test_vectors_kmac.3581441231 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_kmac_xof.511055625
Short name T491
Test name
Test status
Simulation time 727227009 ps
CPU time 6.14 seconds
Started Mar 24 01:59:13 PM PDT 24
Finished Mar 24 01:59:19 PM PDT 24
Peak memory 226704 kb
Host smart-8b30b2f4-147e-4e9d-b3aa-f33118486fe2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511055625 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 13.kmac_test_vectors_kmac_xof.511055625 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_224.1845016371
Short name T263
Test name
Test status
Simulation time 335961018467 ps
CPU time 2311.35 seconds
Started Mar 24 01:59:09 PM PDT 24
Finished Mar 24 02:37:41 PM PDT 24
Peak memory 395744 kb
Host smart-0fd2833e-eac1-4014-89cd-f4852e2d183e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1845016371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_224.1845016371 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_256.1040940195
Short name T1042
Test name
Test status
Simulation time 192527727841 ps
CPU time 2293.7 seconds
Started Mar 24 01:59:14 PM PDT 24
Finished Mar 24 02:37:28 PM PDT 24
Peak memory 390244 kb
Host smart-d69f12c1-8362-4ce6-acc9-f7d91cecfd4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1040940195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_256.1040940195 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_384.3239915432
Short name T731
Test name
Test status
Simulation time 90140828360 ps
CPU time 1483.89 seconds
Started Mar 24 01:59:16 PM PDT 24
Finished Mar 24 02:24:00 PM PDT 24
Peak memory 336196 kb
Host smart-f94b7dfc-748e-4089-84bf-81fd0ad7fc94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3239915432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_384.3239915432 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_sha3_512.26704961
Short name T188
Test name
Test status
Simulation time 178939267659 ps
CPU time 1339.94 seconds
Started Mar 24 01:59:15 PM PDT 24
Finished Mar 24 02:21:35 PM PDT 24
Peak memory 303892 kb
Host smart-b82dcfae-99b6-4947-bbdc-a611c7c0b7c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=26704961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_sha3_512.26704961 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_128.1722472733
Short name T667
Test name
Test status
Simulation time 234501152988 ps
CPU time 6165.17 seconds
Started Mar 24 01:59:15 PM PDT 24
Finished Mar 24 03:42:01 PM PDT 24
Peak memory 654748 kb
Host smart-70c64811-d5be-43fe-bf23-6a371be244fe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1722472733 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_128.1722472733 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/13.kmac_test_vectors_shake_256.3026571515
Short name T415
Test name
Test status
Simulation time 55418291914 ps
CPU time 4254.33 seconds
Started Mar 24 01:59:15 PM PDT 24
Finished Mar 24 03:10:10 PM PDT 24
Peak memory 561408 kb
Host smart-0dbf9ffc-189e-4813-8f7d-17c38d0ac5e7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3026571515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_test_vectors_shake_256.3026571515 +enable_masking=1 +sw_key_masked=0
Directory /workspace/13.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/14.kmac_alert_test.1673126370
Short name T1077
Test name
Test status
Simulation time 162406051 ps
CPU time 0.91 seconds
Started Mar 24 01:59:35 PM PDT 24
Finished Mar 24 01:59:36 PM PDT 24
Peak memory 218480 kb
Host smart-ae3a27e3-ace3-40e4-8b49-ff71506545ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1673126370 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_alert_test.1673126370 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_alert_test/latest

Test location /workspace/coverage/default/14.kmac_app.2264303460
Short name T55
Test name
Test status
Simulation time 9260373678 ps
CPU time 307.65 seconds
Started Mar 24 01:59:31 PM PDT 24
Finished Mar 24 02:04:38 PM PDT 24
Peak memory 246208 kb
Host smart-187298e8-a219-4205-beb8-eb49f5e96129
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264303460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.2264303460 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_app/latest

Test location /workspace/coverage/default/14.kmac_burst_write.2228327131
Short name T1031
Test name
Test status
Simulation time 83556793323 ps
CPU time 1455.42 seconds
Started Mar 24 01:59:24 PM PDT 24
Finished Mar 24 02:23:40 PM PDT 24
Peak memory 239680 kb
Host smart-7874cf72-0864-438a-a4f8-5efabf76ba86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228327131 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.2228327131 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_burst_write/latest

Test location /workspace/coverage/default/14.kmac_edn_timeout_error.1015265184
Short name T246
Test name
Test status
Simulation time 1025759094 ps
CPU time 46.39 seconds
Started Mar 24 01:59:31 PM PDT 24
Finished Mar 24 02:00:17 PM PDT 24
Peak memory 228136 kb
Host smart-4956735f-603c-4ec8-b4b3-0398d2f4adb9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1015265184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.1015265184 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_mode_error.3228745785
Short name T670
Test name
Test status
Simulation time 27849521 ps
CPU time 1.07 seconds
Started Mar 24 01:59:30 PM PDT 24
Finished Mar 24 01:59:31 PM PDT 24
Peak memory 221700 kb
Host smart-35a3a7da-ce71-4fb1-8e80-78e4207db397
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3228745785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.3228745785 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/14.kmac_entropy_refresh.3718588253
Short name T1021
Test name
Test status
Simulation time 19149894776 ps
CPU time 402.68 seconds
Started Mar 24 01:59:30 PM PDT 24
Finished Mar 24 02:06:13 PM PDT 24
Peak memory 250796 kb
Host smart-4c36720e-87bf-440e-9a9b-291557552591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718588253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.3718588253 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/14.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/14.kmac_error.34487374
Short name T851
Test name
Test status
Simulation time 1637160106 ps
CPU time 65.36 seconds
Started Mar 24 01:59:31 PM PDT 24
Finished Mar 24 02:00:36 PM PDT 24
Peak memory 243072 kb
Host smart-96e77033-f435-453d-9cd5-6802edfdfa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34487374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.34487374 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_error/latest

Test location /workspace/coverage/default/14.kmac_key_error.2715080112
Short name T101
Test name
Test status
Simulation time 805160366 ps
CPU time 5.06 seconds
Started Mar 24 01:59:29 PM PDT 24
Finished Mar 24 01:59:35 PM PDT 24
Peak memory 218520 kb
Host smart-4daabe9e-54c5-449a-b5e3-51626d82de0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715080112 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.2715080112 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_key_error/latest

Test location /workspace/coverage/default/14.kmac_lc_escalation.3531689508
Short name T60
Test name
Test status
Simulation time 53611440 ps
CPU time 1.48 seconds
Started Mar 24 01:59:31 PM PDT 24
Finished Mar 24 01:59:33 PM PDT 24
Peak memory 218644 kb
Host smart-d74590b2-53b4-40d8-90a4-ec7e353c2d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531689508 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.3531689508 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/14.kmac_lc_escalation/latest

Test location /workspace/coverage/default/14.kmac_long_msg_and_output.1223000165
Short name T287
Test name
Test status
Simulation time 20874144177 ps
CPU time 2177.36 seconds
Started Mar 24 01:59:22 PM PDT 24
Finished Mar 24 02:35:39 PM PDT 24
Peak memory 417184 kb
Host smart-f888c4c2-5432-4fbe-97be-9b0accbe5958
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223000165 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_a
nd_output.1223000165 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/14.kmac_sideload.302305375
Short name T227
Test name
Test status
Simulation time 2494246859 ps
CPU time 63.6 seconds
Started Mar 24 01:59:21 PM PDT 24
Finished Mar 24 02:00:25 PM PDT 24
Peak memory 225920 kb
Host smart-f2091c6c-2534-4cff-8408-2794f7b4e2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302305375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.302305375 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_sideload/latest

Test location /workspace/coverage/default/14.kmac_smoke.3325091855
Short name T392
Test name
Test status
Simulation time 5567187255 ps
CPU time 60.19 seconds
Started Mar 24 01:59:18 PM PDT 24
Finished Mar 24 02:00:18 PM PDT 24
Peak memory 226812 kb
Host smart-3b512624-fc90-45cd-a9b8-0168d553a4b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325091855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.3325091855 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_smoke/latest

Test location /workspace/coverage/default/14.kmac_stress_all_with_rand_reset.1269112125
Short name T119
Test name
Test status
Simulation time 24459898580 ps
CPU time 248.32 seconds
Started Mar 24 01:59:36 PM PDT 24
Finished Mar 24 02:03:45 PM PDT 24
Peak memory 251392 kb
Host smart-132e2c64-56b3-4c8c-a3d5-2939dacbd2af
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1269112125 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_stress_all_with_rand_reset.1269112125 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac.915146429
Short name T553
Test name
Test status
Simulation time 919994422 ps
CPU time 6.12 seconds
Started Mar 24 01:59:26 PM PDT 24
Finished Mar 24 01:59:32 PM PDT 24
Peak memory 219584 kb
Host smart-32f9ac67-6909-49e4-adbe-5d4a662999d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915146429 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 14.kmac_test_vectors_kmac.915146429 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_kmac_xof.1858488888
Short name T1054
Test name
Test status
Simulation time 1182630755 ps
CPU time 6.04 seconds
Started Mar 24 01:59:26 PM PDT 24
Finished Mar 24 01:59:33 PM PDT 24
Peak memory 218640 kb
Host smart-6edb1363-2c2a-4899-8608-0bc12d2f7617
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858488888 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 14.kmac_test_vectors_kmac_xof.1858488888 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_224.3114256279
Short name T207
Test name
Test status
Simulation time 66161013603 ps
CPU time 2251.01 seconds
Started Mar 24 01:59:20 PM PDT 24
Finished Mar 24 02:36:52 PM PDT 24
Peak memory 397232 kb
Host smart-3f46cdb9-4601-46b6-b701-47478b611682
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3114256279 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_224.3114256279 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_256.959518777
Short name T257
Test name
Test status
Simulation time 253934930409 ps
CPU time 2187.74 seconds
Started Mar 24 01:59:24 PM PDT 24
Finished Mar 24 02:35:52 PM PDT 24
Peak memory 380772 kb
Host smart-b1a6772b-20f0-495a-8471-e9658c481f2b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=959518777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_256.959518777 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_384.503543161
Short name T201
Test name
Test status
Simulation time 55072745008 ps
CPU time 1633.64 seconds
Started Mar 24 01:59:26 PM PDT 24
Finished Mar 24 02:26:40 PM PDT 24
Peak memory 339380 kb
Host smart-7d050416-8120-4143-819f-3df3c7f98ab7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=503543161 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_384.503543161 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_sha3_512.2606650516
Short name T186
Test name
Test status
Simulation time 43609310387 ps
CPU time 1345.58 seconds
Started Mar 24 01:59:25 PM PDT 24
Finished Mar 24 02:21:51 PM PDT 24
Peak memory 299232 kb
Host smart-e5ffd559-7299-4393-b2b2-d0a08ad4d697
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2606650516 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_sha3_512.2606650516 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_128.3338392647
Short name T502
Test name
Test status
Simulation time 339246841738 ps
CPU time 5937.02 seconds
Started Mar 24 01:59:25 PM PDT 24
Finished Mar 24 03:38:23 PM PDT 24
Peak memory 653748 kb
Host smart-41c0edef-140a-4031-92dc-5b6847b031ac
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3338392647 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_128.3338392647 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/14.kmac_test_vectors_shake_256.3105739597
Short name T546
Test name
Test status
Simulation time 712310253196 ps
CPU time 5199.24 seconds
Started Mar 24 01:59:25 PM PDT 24
Finished Mar 24 03:26:04 PM PDT 24
Peak memory 568292 kb
Host smart-ccde7b76-ae30-464b-a5c7-cdb4677542b6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3105739597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_test_vectors_shake_256.3105739597 +enable_masking=1 +sw_key_masked=0
Directory /workspace/14.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/15.kmac_alert_test.3839784924
Short name T347
Test name
Test status
Simulation time 64553856 ps
CPU time 0.77 seconds
Started Mar 24 01:59:51 PM PDT 24
Finished Mar 24 01:59:52 PM PDT 24
Peak memory 218480 kb
Host smart-a571f62f-72c6-4ab7-a773-6596f8cd8a8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839784924 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_alert_test.3839784924 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_alert_test/latest

Test location /workspace/coverage/default/15.kmac_app.1110031699
Short name T280
Test name
Test status
Simulation time 9235016033 ps
CPU time 176.29 seconds
Started Mar 24 01:59:39 PM PDT 24
Finished Mar 24 02:02:36 PM PDT 24
Peak memory 238952 kb
Host smart-6223d611-c507-4014-82a3-dd716b5c7802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110031699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.1110031699 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_app/latest

Test location /workspace/coverage/default/15.kmac_edn_timeout_error.2236904381
Short name T552
Test name
Test status
Simulation time 915733548 ps
CPU time 12.2 seconds
Started Mar 24 01:59:44 PM PDT 24
Finished Mar 24 01:59:57 PM PDT 24
Peak memory 220160 kb
Host smart-69592a38-f2bd-4b87-b287-9666d93feca4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2236904381 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.2236904381 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_mode_error.2375491397
Short name T1073
Test name
Test status
Simulation time 61340436 ps
CPU time 1.08 seconds
Started Mar 24 01:59:43 PM PDT 24
Finished Mar 24 01:59:44 PM PDT 24
Peak memory 222072 kb
Host smart-ba068062-3ecc-4e5f-9b6c-57f74503d045
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2375491397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.2375491397 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/15.kmac_entropy_refresh.894953234
Short name T515
Test name
Test status
Simulation time 7447436888 ps
CPU time 316.22 seconds
Started Mar 24 01:59:39 PM PDT 24
Finished Mar 24 02:04:56 PM PDT 24
Peak memory 248176 kb
Host smart-7f21f611-fa90-447c-a64d-55280de6ca32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894953234 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.894953234 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/15.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/15.kmac_error.1220502970
Short name T601
Test name
Test status
Simulation time 27260576055 ps
CPU time 286.19 seconds
Started Mar 24 01:59:41 PM PDT 24
Finished Mar 24 02:04:27 PM PDT 24
Peak memory 258252 kb
Host smart-befe4206-bdda-4e4a-bccd-301100aa9fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220502970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.1220502970 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_error/latest

Test location /workspace/coverage/default/15.kmac_key_error.200564817
Short name T461
Test name
Test status
Simulation time 21128433 ps
CPU time 0.94 seconds
Started Mar 24 01:59:39 PM PDT 24
Finished Mar 24 01:59:40 PM PDT 24
Peak memory 218352 kb
Host smart-fb57af42-5024-4fbf-a3ea-ebfe072c3ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200564817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.200564817 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_key_error/latest

Test location /workspace/coverage/default/15.kmac_lc_escalation.2766692432
Short name T715
Test name
Test status
Simulation time 960992337 ps
CPU time 27.15 seconds
Started Mar 24 01:59:46 PM PDT 24
Finished Mar 24 02:00:13 PM PDT 24
Peak memory 240168 kb
Host smart-032d4302-2b37-4e31-b552-c187f35ec77f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766692432 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.2766692432 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/15.kmac_lc_escalation/latest

Test location /workspace/coverage/default/15.kmac_long_msg_and_output.2979755577
Short name T544
Test name
Test status
Simulation time 22466310308 ps
CPU time 588.08 seconds
Started Mar 24 01:59:37 PM PDT 24
Finished Mar 24 02:09:25 PM PDT 24
Peak memory 265520 kb
Host smart-2f5372ca-bcad-46e8-aebb-e5bfb3b4e214
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979755577 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_a
nd_output.2979755577 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/15.kmac_sideload.1128723235
Short name T1009
Test name
Test status
Simulation time 11959850972 ps
CPU time 197.2 seconds
Started Mar 24 01:59:35 PM PDT 24
Finished Mar 24 02:02:52 PM PDT 24
Peak memory 241580 kb
Host smart-545736d4-2978-42bf-811c-4763445b3b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128723235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.1128723235 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_sideload/latest

Test location /workspace/coverage/default/15.kmac_smoke.3591281249
Short name T202
Test name
Test status
Simulation time 2075908799 ps
CPU time 81.29 seconds
Started Mar 24 01:59:35 PM PDT 24
Finished Mar 24 02:00:57 PM PDT 24
Peak memory 226688 kb
Host smart-3ba72a3e-e3ec-49ff-892b-5ee9b412b8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591281249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.3591281249 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_smoke/latest

Test location /workspace/coverage/default/15.kmac_stress_all.1143562623
Short name T679
Test name
Test status
Simulation time 2451731985 ps
CPU time 160.95 seconds
Started Mar 24 01:59:44 PM PDT 24
Finished Mar 24 02:02:25 PM PDT 24
Peak memory 247532 kb
Host smart-98ce28ef-17d5-4ead-bc19-998161f62156
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1143562623 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_stress_all.1143562623 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_stress_all/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac.2988283574
Short name T980
Test name
Test status
Simulation time 212864896 ps
CPU time 5.81 seconds
Started Mar 24 01:59:42 PM PDT 24
Finished Mar 24 01:59:47 PM PDT 24
Peak memory 218532 kb
Host smart-6a99dd97-5d77-478a-9b63-eae05e05775c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988283574 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 15.kmac_test_vectors_kmac.2988283574 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_kmac_xof.3207018809
Short name T536
Test name
Test status
Simulation time 370185634 ps
CPU time 7.05 seconds
Started Mar 24 01:59:40 PM PDT 24
Finished Mar 24 01:59:47 PM PDT 24
Peak memory 218652 kb
Host smart-27c7065f-65e8-4e09-9216-839e89526a81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207018809 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 15.kmac_test_vectors_kmac_xof.3207018809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_224.3708303183
Short name T637
Test name
Test status
Simulation time 21126204587 ps
CPU time 2057.12 seconds
Started Mar 24 01:59:35 PM PDT 24
Finished Mar 24 02:33:53 PM PDT 24
Peak memory 397456 kb
Host smart-b6430a1c-1dcf-44a9-a0de-f4f1a7f7fbea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3708303183 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_224.3708303183 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_256.1902081571
Short name T966
Test name
Test status
Simulation time 19704786506 ps
CPU time 1907.9 seconds
Started Mar 24 01:59:41 PM PDT 24
Finished Mar 24 02:31:29 PM PDT 24
Peak memory 387700 kb
Host smart-4829c36b-c04b-49fb-9c65-90ab35d48cff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1902081571 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_256.1902081571 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_384.3839732077
Short name T640
Test name
Test status
Simulation time 59054711788 ps
CPU time 1504.51 seconds
Started Mar 24 01:59:40 PM PDT 24
Finished Mar 24 02:24:45 PM PDT 24
Peak memory 340280 kb
Host smart-a10a83f0-3330-43c3-8a5c-964b24a30af5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3839732077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_384.3839732077 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_sha3_512.31409335
Short name T18
Test name
Test status
Simulation time 10521148582 ps
CPU time 1139.55 seconds
Started Mar 24 01:59:41 PM PDT 24
Finished Mar 24 02:18:41 PM PDT 24
Peak memory 297156 kb
Host smart-c51bab99-c41e-4712-a461-2fbc8b7ce5ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=31409335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_sha3_512.31409335 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_128.3006513557
Short name T987
Test name
Test status
Simulation time 746318956667 ps
CPU time 5986.57 seconds
Started Mar 24 01:59:41 PM PDT 24
Finished Mar 24 03:39:29 PM PDT 24
Peak memory 661912 kb
Host smart-e611b17a-c2cc-44ee-a3ec-a92292114e5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3006513557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_128.3006513557 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/15.kmac_test_vectors_shake_256.1843931982
Short name T791
Test name
Test status
Simulation time 219023517415 ps
CPU time 4576.77 seconds
Started Mar 24 01:59:39 PM PDT 24
Finished Mar 24 03:15:56 PM PDT 24
Peak memory 572928 kb
Host smart-d9d651b6-2ced-49f2-9166-0cb30bda2ba1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1843931982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_test_vectors_shake_256.1843931982 +enable_masking=1 +sw_key_masked=0
Directory /workspace/15.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/16.kmac_alert_test.1880314842
Short name T313
Test name
Test status
Simulation time 90692097 ps
CPU time 0.93 seconds
Started Mar 24 02:00:00 PM PDT 24
Finished Mar 24 02:00:01 PM PDT 24
Peak memory 218468 kb
Host smart-72bd885d-aecb-490b-90d7-e742a8749bb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1880314842 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_alert_test.1880314842 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_alert_test/latest

Test location /workspace/coverage/default/16.kmac_app.3053465462
Short name T295
Test name
Test status
Simulation time 51680921914 ps
CPU time 268.31 seconds
Started Mar 24 01:59:53 PM PDT 24
Finished Mar 24 02:04:21 PM PDT 24
Peak memory 246056 kb
Host smart-2003884b-8204-4763-88f6-1011b4f006d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3053465462 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.3053465462 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_app/latest

Test location /workspace/coverage/default/16.kmac_burst_write.761630066
Short name T300
Test name
Test status
Simulation time 58116608007 ps
CPU time 518.26 seconds
Started Mar 24 01:59:50 PM PDT 24
Finished Mar 24 02:08:28 PM PDT 24
Peak memory 235360 kb
Host smart-29c3bb02-07ce-4dfe-b9f7-3c4f6f3f80b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761630066 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.761630066 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_burst_write/latest

Test location /workspace/coverage/default/16.kmac_edn_timeout_error.3415977720
Short name T388
Test name
Test status
Simulation time 1142977337 ps
CPU time 38.2 seconds
Started Mar 24 01:59:57 PM PDT 24
Finished Mar 24 02:00:36 PM PDT 24
Peak memory 226468 kb
Host smart-ac5d939f-1338-4a15-aa53-9276243e07db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3415977720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.3415977720 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_mode_error.2247216799
Short name T998
Test name
Test status
Simulation time 20026433 ps
CPU time 1 seconds
Started Mar 24 02:00:01 PM PDT 24
Finished Mar 24 02:00:03 PM PDT 24
Peak memory 220448 kb
Host smart-316f48ac-9b72-469e-a409-df99af6eb3da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2247216799 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.2247216799 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/16.kmac_entropy_refresh.1565007813
Short name T469
Test name
Test status
Simulation time 31214490201 ps
CPU time 351.69 seconds
Started Mar 24 01:59:53 PM PDT 24
Finished Mar 24 02:05:45 PM PDT 24
Peak memory 252224 kb
Host smart-eaae31db-21d6-4e47-b3b8-6c12489b5cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565007813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.1565007813 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/16.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/16.kmac_error.2062291812
Short name T761
Test name
Test status
Simulation time 36499937841 ps
CPU time 304.38 seconds
Started Mar 24 01:59:54 PM PDT 24
Finished Mar 24 02:04:59 PM PDT 24
Peak memory 251352 kb
Host smart-912e3bdd-90e9-4e59-9d7a-dc0051880ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062291812 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.2062291812 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_error/latest

Test location /workspace/coverage/default/16.kmac_long_msg_and_output.284985058
Short name T219
Test name
Test status
Simulation time 57191027874 ps
CPU time 2007.3 seconds
Started Mar 24 01:59:48 PM PDT 24
Finished Mar 24 02:33:16 PM PDT 24
Peak memory 397776 kb
Host smart-dccfbef3-82a1-432a-89b0-1412b27e1431
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284985058 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_an
d_output.284985058 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/16.kmac_sideload.3821844472
Short name T1004
Test name
Test status
Simulation time 49540848852 ps
CPU time 416.51 seconds
Started Mar 24 01:59:51 PM PDT 24
Finished Mar 24 02:06:48 PM PDT 24
Peak memory 251512 kb
Host smart-207f5539-c20a-4ec6-b446-639c1a7002ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821844472 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.3821844472 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_sideload/latest

Test location /workspace/coverage/default/16.kmac_smoke.1676250982
Short name T1072
Test name
Test status
Simulation time 40558641165 ps
CPU time 62.05 seconds
Started Mar 24 01:59:49 PM PDT 24
Finished Mar 24 02:00:52 PM PDT 24
Peak memory 226820 kb
Host smart-ac2ca7f5-c7ae-4602-b13a-c12edf1b79b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676250982 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.1676250982 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_smoke/latest

Test location /workspace/coverage/default/16.kmac_stress_all.579817553
Short name T320
Test name
Test status
Simulation time 15003098218 ps
CPU time 514.75 seconds
Started Mar 24 02:00:01 PM PDT 24
Finished Mar 24 02:08:36 PM PDT 24
Peak memory 284128 kb
Host smart-2d9b036e-ea48-45b7-a050-bfd48b5f5083
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=579817553 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_stress_all.579817553 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_stress_all/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac.2630026805
Short name T567
Test name
Test status
Simulation time 426512851 ps
CPU time 6.14 seconds
Started Mar 24 01:59:53 PM PDT 24
Finished Mar 24 02:00:00 PM PDT 24
Peak memory 226776 kb
Host smart-d529cccd-1454-4de9-8f6c-a6f585a3f0d4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630026805 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 16.kmac_test_vectors_kmac.2630026805 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_kmac_xof.154913158
Short name T780
Test name
Test status
Simulation time 252027032 ps
CPU time 6.24 seconds
Started Mar 24 01:59:54 PM PDT 24
Finished Mar 24 02:00:01 PM PDT 24
Peak memory 226672 kb
Host smart-e7a5ad8f-720d-4a28-92a8-547b97b22771
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154913158 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 16.kmac_test_vectors_kmac_xof.154913158 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_224.4248730865
Short name T839
Test name
Test status
Simulation time 21712598870 ps
CPU time 1775.6 seconds
Started Mar 24 01:59:49 PM PDT 24
Finished Mar 24 02:29:26 PM PDT 24
Peak memory 400692 kb
Host smart-a183a0a4-5af5-4db5-a351-34f90a49e0ce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4248730865 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_224.4248730865 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_256.497259444
Short name T341
Test name
Test status
Simulation time 1005338196646 ps
CPU time 2264.33 seconds
Started Mar 24 01:59:54 PM PDT 24
Finished Mar 24 02:37:39 PM PDT 24
Peak memory 382968 kb
Host smart-38c2b14e-7800-40e8-930a-e63e000e4d7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=497259444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_256.497259444 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_384.1833991412
Short name T984
Test name
Test status
Simulation time 48033218794 ps
CPU time 1776.24 seconds
Started Mar 24 01:59:53 PM PDT 24
Finished Mar 24 02:29:30 PM PDT 24
Peak memory 338448 kb
Host smart-6902a627-b627-40dc-97d4-af8b19ae9faf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1833991412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_384.1833991412 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_sha3_512.1872844731
Short name T928
Test name
Test status
Simulation time 51409155130 ps
CPU time 1314.4 seconds
Started Mar 24 01:59:53 PM PDT 24
Finished Mar 24 02:21:48 PM PDT 24
Peak memory 299396 kb
Host smart-3034195b-05b8-4f19-af21-54abc6d4a19f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1872844731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_sha3_512.1872844731 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_128.45199075
Short name T240
Test name
Test status
Simulation time 538762242116 ps
CPU time 5867.88 seconds
Started Mar 24 01:59:53 PM PDT 24
Finished Mar 24 03:37:42 PM PDT 24
Peak memory 648716 kb
Host smart-d2c58afc-978a-4235-9c52-8602d99aef87
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=45199075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_128.45199075 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/16.kmac_test_vectors_shake_256.3842083440
Short name T245
Test name
Test status
Simulation time 911009171181 ps
CPU time 5529.62 seconds
Started Mar 24 01:59:54 PM PDT 24
Finished Mar 24 03:32:04 PM PDT 24
Peak memory 563644 kb
Host smart-df40972a-d6cc-4891-891e-e71e9ac4cdda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3842083440 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_test_vectors_shake_256.3842083440 +enable_masking=1 +sw_key_masked=0
Directory /workspace/16.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/17.kmac_alert_test.245766436
Short name T914
Test name
Test status
Simulation time 16148398 ps
CPU time 0.79 seconds
Started Mar 24 02:00:21 PM PDT 24
Finished Mar 24 02:00:24 PM PDT 24
Peak memory 218488 kb
Host smart-dd1e6446-e1e4-4964-814b-f033e602d759
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245766436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_alert_test.245766436 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/17.kmac_alert_test/latest

Test location /workspace/coverage/default/17.kmac_app.2031101598
Short name T264
Test name
Test status
Simulation time 11947129378 ps
CPU time 222.64 seconds
Started Mar 24 02:00:11 PM PDT 24
Finished Mar 24 02:03:54 PM PDT 24
Peak memory 242760 kb
Host smart-e8ab3e22-36da-41a5-be34-9d3384fbbcab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031101598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.2031101598 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_app/latest

Test location /workspace/coverage/default/17.kmac_burst_write.2331113740
Short name T1049
Test name
Test status
Simulation time 29774527853 ps
CPU time 1521.76 seconds
Started Mar 24 02:00:11 PM PDT 24
Finished Mar 24 02:25:33 PM PDT 24
Peak memory 243168 kb
Host smart-db3450d3-1bc2-410c-8119-7fb128638b50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331113740 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.2331113740 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_burst_write/latest

Test location /workspace/coverage/default/17.kmac_edn_timeout_error.1847499942
Short name T940
Test name
Test status
Simulation time 578262867 ps
CPU time 17.12 seconds
Started Mar 24 02:00:10 PM PDT 24
Finished Mar 24 02:00:27 PM PDT 24
Peak memory 227940 kb
Host smart-e338b116-8a9f-4e5a-91f1-36f62c84f9a9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1847499942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.1847499942 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_mode_error.3879583689
Short name T70
Test name
Test status
Simulation time 17608638 ps
CPU time 0.92 seconds
Started Mar 24 02:00:16 PM PDT 24
Finished Mar 24 02:00:17 PM PDT 24
Peak memory 221728 kb
Host smart-39e97f2a-5edc-4374-bbc2-790e7302a8fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3879583689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.3879583689 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/17.kmac_entropy_refresh.2798612505
Short name T1038
Test name
Test status
Simulation time 5464386114 ps
CPU time 133.17 seconds
Started Mar 24 02:00:10 PM PDT 24
Finished Mar 24 02:02:23 PM PDT 24
Peak memory 235076 kb
Host smart-0a646aff-6c3f-4576-b8e4-f502be49716e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798612505 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.2798612505 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/17.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/17.kmac_error.587318482
Short name T442
Test name
Test status
Simulation time 533242545 ps
CPU time 14.65 seconds
Started Mar 24 02:00:10 PM PDT 24
Finished Mar 24 02:00:25 PM PDT 24
Peak memory 242328 kb
Host smart-1637bdc8-b59c-47b9-bcc4-bdb6e6720c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587318482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.587318482 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_error/latest

Test location /workspace/coverage/default/17.kmac_key_error.2367994731
Short name T634
Test name
Test status
Simulation time 393752270 ps
CPU time 2.89 seconds
Started Mar 24 02:00:10 PM PDT 24
Finished Mar 24 02:00:13 PM PDT 24
Peak memory 218512 kb
Host smart-3b945b7e-91b2-4f37-87bb-56fbb9863137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367994731 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.2367994731 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_key_error/latest

Test location /workspace/coverage/default/17.kmac_lc_escalation.735107977
Short name T75
Test name
Test status
Simulation time 141460641 ps
CPU time 1.57 seconds
Started Mar 24 02:00:16 PM PDT 24
Finished Mar 24 02:00:18 PM PDT 24
Peak memory 221920 kb
Host smart-afaf09f9-74b0-4770-9b28-e035d4195aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735107977 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.735107977 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/17.kmac_lc_escalation/latest

Test location /workspace/coverage/default/17.kmac_long_msg_and_output.3104827976
Short name T979
Test name
Test status
Simulation time 68361580068 ps
CPU time 2537.32 seconds
Started Mar 24 02:00:07 PM PDT 24
Finished Mar 24 02:42:25 PM PDT 24
Peak memory 423328 kb
Host smart-f9ac5189-c0fa-4954-8e66-1d7655c6b9fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104827976 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_a
nd_output.3104827976 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/17.kmac_sideload.2809314247
Short name T737
Test name
Test status
Simulation time 5183328685 ps
CPU time 382.28 seconds
Started Mar 24 02:00:08 PM PDT 24
Finished Mar 24 02:06:31 PM PDT 24
Peak memory 252880 kb
Host smart-c5cf4201-5ed8-4be7-b8c1-4a4a034efe16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809314247 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.2809314247 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_sideload/latest

Test location /workspace/coverage/default/17.kmac_smoke.1533555278
Short name T724
Test name
Test status
Simulation time 2090839043 ps
CPU time 13.45 seconds
Started Mar 24 02:00:06 PM PDT 24
Finished Mar 24 02:00:19 PM PDT 24
Peak memory 223532 kb
Host smart-42aa49f6-99cd-4002-97c7-cd8da858deb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533555278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.1533555278 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_smoke/latest

Test location /workspace/coverage/default/17.kmac_stress_all_with_rand_reset.2152756763
Short name T756
Test name
Test status
Simulation time 46484591431 ps
CPU time 284.51 seconds
Started Mar 24 02:00:16 PM PDT 24
Finished Mar 24 02:05:01 PM PDT 24
Peak memory 255804 kb
Host smart-02341142-b6fe-4ced-a582-d812c42a6691
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2152756763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_stress_all_with_rand_reset.2152756763 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac.392053864
Short name T712
Test name
Test status
Simulation time 420004411 ps
CPU time 6.4 seconds
Started Mar 24 02:00:10 PM PDT 24
Finished Mar 24 02:00:17 PM PDT 24
Peak memory 226724 kb
Host smart-66b3147d-3517-4f32-8267-c9499142b8a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392053864 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 17.kmac_test_vectors_kmac.392053864 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_kmac_xof.2775218114
Short name T609
Test name
Test status
Simulation time 1180456399 ps
CPU time 5.63 seconds
Started Mar 24 02:00:10 PM PDT 24
Finished Mar 24 02:00:16 PM PDT 24
Peak memory 218620 kb
Host smart-d4036dc4-6575-4ca7-9a7f-b6d0da217262
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775218114 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 17.kmac_test_vectors_kmac_xof.2775218114 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_224.3744749957
Short name T965
Test name
Test status
Simulation time 131954193623 ps
CPU time 2213.64 seconds
Started Mar 24 02:00:09 PM PDT 24
Finished Mar 24 02:37:04 PM PDT 24
Peak memory 390572 kb
Host smart-7d5a035a-337c-4d52-be8b-9cec446a743b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3744749957 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_224.3744749957 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_256.1036319209
Short name T217
Test name
Test status
Simulation time 78358009067 ps
CPU time 1980.96 seconds
Started Mar 24 02:00:09 PM PDT 24
Finished Mar 24 02:33:10 PM PDT 24
Peak memory 394936 kb
Host smart-f607f3e8-3f78-4f03-8634-97dc74a6744b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1036319209 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_256.1036319209 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_384.1226417968
Short name T605
Test name
Test status
Simulation time 200045855190 ps
CPU time 1639.07 seconds
Started Mar 24 02:00:09 PM PDT 24
Finished Mar 24 02:27:28 PM PDT 24
Peak memory 338896 kb
Host smart-e569a63f-f301-41ec-971e-784cfb95d294
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1226417968 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_384.1226417968 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_sha3_512.1403425273
Short name T971
Test name
Test status
Simulation time 11170101665 ps
CPU time 1270.06 seconds
Started Mar 24 02:00:10 PM PDT 24
Finished Mar 24 02:21:20 PM PDT 24
Peak memory 298240 kb
Host smart-895d0674-6e2d-4b34-bf8c-75ee62f75138
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1403425273 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_sha3_512.1403425273 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_128.342838362
Short name T531
Test name
Test status
Simulation time 294902535735 ps
CPU time 5718.62 seconds
Started Mar 24 02:00:11 PM PDT 24
Finished Mar 24 03:35:30 PM PDT 24
Peak memory 657408 kb
Host smart-b447d3e3-716a-4a20-a784-6952acb83f91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=342838362 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_128.342838362 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/17.kmac_test_vectors_shake_256.3583090663
Short name T947
Test name
Test status
Simulation time 387981396123 ps
CPU time 5168.92 seconds
Started Mar 24 02:00:10 PM PDT 24
Finished Mar 24 03:26:20 PM PDT 24
Peak memory 573876 kb
Host smart-f8b54e01-dc82-4fc6-b393-50c97ff9ff10
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3583090663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_test_vectors_shake_256.3583090663 +enable_masking=1 +sw_key_masked=0
Directory /workspace/17.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/18.kmac_alert_test.2237051537
Short name T580
Test name
Test status
Simulation time 41714644 ps
CPU time 0.83 seconds
Started Mar 24 02:00:35 PM PDT 24
Finished Mar 24 02:00:36 PM PDT 24
Peak memory 220508 kb
Host smart-b4fa1efe-8c9b-4952-b407-5f2d63056287
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237051537 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_alert_test.2237051537 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_alert_test/latest

Test location /workspace/coverage/default/18.kmac_app.2258871813
Short name T760
Test name
Test status
Simulation time 15071578916 ps
CPU time 157.95 seconds
Started Mar 24 02:00:27 PM PDT 24
Finished Mar 24 02:03:06 PM PDT 24
Peak memory 239724 kb
Host smart-c341955a-dc6f-4e70-9c4b-b2860ea53cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258871813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.2258871813 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_app/latest

Test location /workspace/coverage/default/18.kmac_burst_write.825957427
Short name T239
Test name
Test status
Simulation time 5279336663 ps
CPU time 118.62 seconds
Started Mar 24 02:00:18 PM PDT 24
Finished Mar 24 02:02:17 PM PDT 24
Peak memory 243168 kb
Host smart-87017355-5146-40b9-8685-a9cbf1f6674d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825957427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.825957427 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_burst_write/latest

Test location /workspace/coverage/default/18.kmac_edn_timeout_error.1164301101
Short name T646
Test name
Test status
Simulation time 3268973645 ps
CPU time 41.27 seconds
Started Mar 24 02:00:31 PM PDT 24
Finished Mar 24 02:01:12 PM PDT 24
Peak memory 227052 kb
Host smart-14b2b4b4-409c-4500-8deb-b5744385aa18
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1164301101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.1164301101 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_mode_error.2800929869
Short name T549
Test name
Test status
Simulation time 40055046 ps
CPU time 0.91 seconds
Started Mar 24 02:00:32 PM PDT 24
Finished Mar 24 02:00:33 PM PDT 24
Peak memory 220484 kb
Host smart-9f6dad3f-629b-4d6e-8181-d4ecc9db1543
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2800929869 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.2800929869 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/18.kmac_entropy_refresh.3369350110
Short name T886
Test name
Test status
Simulation time 20009191770 ps
CPU time 392.47 seconds
Started Mar 24 02:00:32 PM PDT 24
Finished Mar 24 02:07:05 PM PDT 24
Peak memory 253880 kb
Host smart-b281d3f9-9323-42d2-9424-15245fbd2e86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369350110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.3369350110 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/18.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/18.kmac_error.355183230
Short name T938
Test name
Test status
Simulation time 63613648478 ps
CPU time 299.4 seconds
Started Mar 24 02:00:31 PM PDT 24
Finished Mar 24 02:05:31 PM PDT 24
Peak memory 253556 kb
Host smart-bb135204-fc61-4930-97c5-c37e2dd4de28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355183230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.355183230 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_error/latest

Test location /workspace/coverage/default/18.kmac_key_error.2016779481
Short name T383
Test name
Test status
Simulation time 101839558 ps
CPU time 1.29 seconds
Started Mar 24 02:00:32 PM PDT 24
Finished Mar 24 02:00:33 PM PDT 24
Peak memory 218348 kb
Host smart-6930e9e1-1d4e-4cea-90f4-77187edae878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016779481 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.2016779481 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_key_error/latest

Test location /workspace/coverage/default/18.kmac_lc_escalation.2967376485
Short name T703
Test name
Test status
Simulation time 1134450143 ps
CPU time 41.48 seconds
Started Mar 24 02:00:33 PM PDT 24
Finished Mar 24 02:01:14 PM PDT 24
Peak memory 235460 kb
Host smart-a89b666e-5ab8-4e7e-a79c-1e5efce048a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967376485 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.2967376485 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/18.kmac_lc_escalation/latest

Test location /workspace/coverage/default/18.kmac_long_msg_and_output.3376988281
Short name T611
Test name
Test status
Simulation time 207484504376 ps
CPU time 1876.34 seconds
Started Mar 24 02:00:21 PM PDT 24
Finished Mar 24 02:31:40 PM PDT 24
Peak memory 377132 kb
Host smart-50ec784a-5e14-4d29-92d4-a22180ef6f82
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376988281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_a
nd_output.3376988281 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/18.kmac_sideload.2938834934
Short name T484
Test name
Test status
Simulation time 7540664069 ps
CPU time 206.41 seconds
Started Mar 24 02:00:19 PM PDT 24
Finished Mar 24 02:03:46 PM PDT 24
Peak memory 238744 kb
Host smart-9fc4c83c-eb92-45f1-8619-278e893702bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938834934 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.2938834934 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_sideload/latest

Test location /workspace/coverage/default/18.kmac_smoke.2040209134
Short name T471
Test name
Test status
Simulation time 17467975668 ps
CPU time 49.78 seconds
Started Mar 24 02:00:18 PM PDT 24
Finished Mar 24 02:01:08 PM PDT 24
Peak memory 226724 kb
Host smart-76d25ced-c475-482f-9ce8-6219f9da0751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040209134 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.2040209134 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_smoke/latest

Test location /workspace/coverage/default/18.kmac_stress_all.321933302
Short name T385
Test name
Test status
Simulation time 11602370812 ps
CPU time 105.71 seconds
Started Mar 24 02:00:30 PM PDT 24
Finished Mar 24 02:02:16 PM PDT 24
Peak memory 251364 kb
Host smart-e8c71a63-3ae3-41fc-ab75-bcda9a124395
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=321933302 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_stress_all.321933302 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_stress_all/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac.3368952581
Short name T917
Test name
Test status
Simulation time 151060225 ps
CPU time 5.79 seconds
Started Mar 24 02:00:28 PM PDT 24
Finished Mar 24 02:00:34 PM PDT 24
Peak memory 226740 kb
Host smart-155f55fd-3b2f-4e32-9330-f32207d49983
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368952581 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 18.kmac_test_vectors_kmac.3368952581 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_kmac_xof.3331970319
Short name T351
Test name
Test status
Simulation time 119931302 ps
CPU time 5.58 seconds
Started Mar 24 02:00:28 PM PDT 24
Finished Mar 24 02:00:34 PM PDT 24
Peak memory 218672 kb
Host smart-9fdcf9bf-afb6-4d7e-a3a6-8e94f4dd7383
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331970319 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 18.kmac_test_vectors_kmac_xof.3331970319 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_224.1865490780
Short name T14
Test name
Test status
Simulation time 68144075716 ps
CPU time 2335.06 seconds
Started Mar 24 02:00:18 PM PDT 24
Finished Mar 24 02:39:13 PM PDT 24
Peak memory 404416 kb
Host smart-cda82132-6e6a-490c-93d1-9d4d3d80d2a4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1865490780 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_224.1865490780 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_256.2454131154
Short name T107
Test name
Test status
Simulation time 18898644355 ps
CPU time 1735.92 seconds
Started Mar 24 02:00:18 PM PDT 24
Finished Mar 24 02:29:15 PM PDT 24
Peak memory 374528 kb
Host smart-a733cf8d-41fb-490c-8f08-8c0bbde3691f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2454131154 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_256.2454131154 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_384.3446269564
Short name T669
Test name
Test status
Simulation time 52762184609 ps
CPU time 1786.71 seconds
Started Mar 24 02:00:18 PM PDT 24
Finished Mar 24 02:30:06 PM PDT 24
Peak memory 350020 kb
Host smart-b07d09df-3430-403d-95bd-32862ea10e96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3446269564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_384.3446269564 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_sha3_512.467632936
Short name T951
Test name
Test status
Simulation time 227770211081 ps
CPU time 1276.47 seconds
Started Mar 24 02:00:23 PM PDT 24
Finished Mar 24 02:21:40 PM PDT 24
Peak memory 305136 kb
Host smart-6b22737d-c14d-4941-a7b1-f9d222ee0192
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=467632936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_sha3_512.467632936 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_128.2133797978
Short name T808
Test name
Test status
Simulation time 668013696907 ps
CPU time 6207.43 seconds
Started Mar 24 02:00:24 PM PDT 24
Finished Mar 24 03:43:53 PM PDT 24
Peak memory 674788 kb
Host smart-9f808a83-f8cd-40ec-a6f8-9db6e9427e5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2133797978 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_128.2133797978 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/18.kmac_test_vectors_shake_256.2034182807
Short name T216
Test name
Test status
Simulation time 658308318502 ps
CPU time 4535.93 seconds
Started Mar 24 02:00:24 PM PDT 24
Finished Mar 24 03:16:01 PM PDT 24
Peak memory 567504 kb
Host smart-8d2e3cb2-4ba7-4c6d-b4db-17d6cc8fca33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2034182807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_test_vectors_shake_256.2034182807 +enable_masking=1 +sw_key_masked=0
Directory /workspace/18.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/19.kmac_alert_test.1514457832
Short name T145
Test name
Test status
Simulation time 41603687 ps
CPU time 0.78 seconds
Started Mar 24 02:00:52 PM PDT 24
Finished Mar 24 02:00:53 PM PDT 24
Peak memory 218460 kb
Host smart-c1da8fa7-88af-49d8-873a-7764b9f48c5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514457832 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_alert_test.1514457832 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_alert_test/latest

Test location /workspace/coverage/default/19.kmac_app.2165949355
Short name T510
Test name
Test status
Simulation time 1219442101 ps
CPU time 71.92 seconds
Started Mar 24 02:00:46 PM PDT 24
Finished Mar 24 02:01:58 PM PDT 24
Peak memory 230748 kb
Host smart-23d78171-3d4c-42f6-b5a6-3cc810043fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165949355 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.2165949355 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_app/latest

Test location /workspace/coverage/default/19.kmac_burst_write.625362955
Short name T686
Test name
Test status
Simulation time 88098917749 ps
CPU time 990.19 seconds
Started Mar 24 02:00:35 PM PDT 24
Finished Mar 24 02:17:05 PM PDT 24
Peak memory 243188 kb
Host smart-4aba0604-e5de-4550-b5b8-028cd78f0600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625362955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.625362955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_burst_write/latest

Test location /workspace/coverage/default/19.kmac_edn_timeout_error.1270726736
Short name T485
Test name
Test status
Simulation time 845760258 ps
CPU time 24.55 seconds
Started Mar 24 02:00:50 PM PDT 24
Finished Mar 24 02:01:15 PM PDT 24
Peak memory 225820 kb
Host smart-b0b98830-6d5a-40f8-8edd-fe29cd8bc31f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1270726736 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.1270726736 +enab
le_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_mode_error.35196816
Short name T16
Test name
Test status
Simulation time 47857756 ps
CPU time 1.47 seconds
Started Mar 24 02:00:49 PM PDT 24
Finished Mar 24 02:00:50 PM PDT 24
Peak memory 222256 kb
Host smart-ee2914dd-aa80-4f95-9704-6a7e7ff8c5f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=35196816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.35196816 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/19.kmac_entropy_refresh.2726856743
Short name T677
Test name
Test status
Simulation time 19506742979 ps
CPU time 65.71 seconds
Started Mar 24 02:00:44 PM PDT 24
Finished Mar 24 02:01:50 PM PDT 24
Peak memory 229308 kb
Host smart-2a76204f-80a2-4058-a513-f1cfe40e15b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726856743 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.2726856743 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/19.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/19.kmac_error.1132094675
Short name T809
Test name
Test status
Simulation time 557509146 ps
CPU time 7.04 seconds
Started Mar 24 02:00:43 PM PDT 24
Finished Mar 24 02:00:50 PM PDT 24
Peak memory 226712 kb
Host smart-3b7140b6-b54f-4976-9577-405d1ca475a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132094675 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.1132094675 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_error/latest

Test location /workspace/coverage/default/19.kmac_key_error.3197152124
Short name T446
Test name
Test status
Simulation time 735868479 ps
CPU time 2.6 seconds
Started Mar 24 02:00:43 PM PDT 24
Finished Mar 24 02:00:45 PM PDT 24
Peak memory 218532 kb
Host smart-51f875ce-30be-4b23-a8aa-caee74f4e277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197152124 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.3197152124 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_key_error/latest

Test location /workspace/coverage/default/19.kmac_lc_escalation.596422604
Short name T78
Test name
Test status
Simulation time 124615210 ps
CPU time 1.26 seconds
Started Mar 24 02:00:50 PM PDT 24
Finished Mar 24 02:00:52 PM PDT 24
Peak memory 218620 kb
Host smart-db8f1366-fc0f-423d-9690-12ad14d090ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596422604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.596422604 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/19.kmac_lc_escalation/latest

Test location /workspace/coverage/default/19.kmac_long_msg_and_output.3241247519
Short name T260
Test name
Test status
Simulation time 92751108991 ps
CPU time 2754.24 seconds
Started Mar 24 02:00:35 PM PDT 24
Finished Mar 24 02:46:30 PM PDT 24
Peak memory 436044 kb
Host smart-5a1c4a48-38d5-421a-a149-8334c3ea71d7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241247519 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_a
nd_output.3241247519 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/19.kmac_sideload.749598915
Short name T599
Test name
Test status
Simulation time 3547594659 ps
CPU time 13.2 seconds
Started Mar 24 02:00:34 PM PDT 24
Finished Mar 24 02:00:48 PM PDT 24
Peak memory 226748 kb
Host smart-68362820-a885-488f-be93-d96d0e07da5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=749598915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.749598915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_sideload/latest

Test location /workspace/coverage/default/19.kmac_smoke.2597483696
Short name T873
Test name
Test status
Simulation time 1548864529 ps
CPU time 32.66 seconds
Started Mar 24 02:00:37 PM PDT 24
Finished Mar 24 02:01:10 PM PDT 24
Peak memory 219124 kb
Host smart-004a71fe-dc7d-4660-a310-6e8a1dce40cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597483696 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.2597483696 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_smoke/latest

Test location /workspace/coverage/default/19.kmac_stress_all.1797619392
Short name T276
Test name
Test status
Simulation time 18354079013 ps
CPU time 1344.45 seconds
Started Mar 24 02:00:50 PM PDT 24
Finished Mar 24 02:23:15 PM PDT 24
Peak memory 390520 kb
Host smart-9ccc4718-a3c7-4f1f-8abb-43a647c50666
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1797619392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_stress_all.1797619392 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_stress_all/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac.288073692
Short name T661
Test name
Test status
Simulation time 126029480 ps
CPU time 5.28 seconds
Started Mar 24 02:00:43 PM PDT 24
Finished Mar 24 02:00:48 PM PDT 24
Peak memory 226712 kb
Host smart-f1e37d92-613c-40c7-9177-d0f1f08c6565
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288073692 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 19.kmac_test_vectors_kmac.288073692 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_kmac_xof.1439659841
Short name T779
Test name
Test status
Simulation time 1003548453 ps
CPU time 6.32 seconds
Started Mar 24 02:00:43 PM PDT 24
Finished Mar 24 02:00:49 PM PDT 24
Peak memory 218656 kb
Host smart-e19de3e7-e297-4a56-808f-ea5eb6033ccc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439659841 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 19.kmac_test_vectors_kmac_xof.1439659841 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_224.2486468306
Short name T447
Test name
Test status
Simulation time 67592838414 ps
CPU time 2209.4 seconds
Started Mar 24 02:00:35 PM PDT 24
Finished Mar 24 02:37:24 PM PDT 24
Peak memory 400888 kb
Host smart-117c8959-9ae7-4c08-a26b-6669d338308d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2486468306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_224.2486468306 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_256.1532680813
Short name T774
Test name
Test status
Simulation time 1548723433163 ps
CPU time 2500.22 seconds
Started Mar 24 02:00:34 PM PDT 24
Finished Mar 24 02:42:15 PM PDT 24
Peak memory 392352 kb
Host smart-2fbad2bd-bce2-43f2-94f2-678d34ad79b8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1532680813 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_256.1532680813 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_384.3116269764
Short name T753
Test name
Test status
Simulation time 122618450134 ps
CPU time 1473.98 seconds
Started Mar 24 02:00:40 PM PDT 24
Finished Mar 24 02:25:15 PM PDT 24
Peak memory 339456 kb
Host smart-b053899e-eda5-4670-8aeb-b9f5fa1c7d9f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3116269764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_384.3116269764 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_sha3_512.3954507230
Short name T559
Test name
Test status
Simulation time 216724362546 ps
CPU time 1405.65 seconds
Started Mar 24 02:00:41 PM PDT 24
Finished Mar 24 02:24:07 PM PDT 24
Peak memory 302320 kb
Host smart-10c747c7-cf45-4f02-b13e-8e4fc4d73dda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3954507230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_sha3_512.3954507230 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_128.2338574888
Short name T767
Test name
Test status
Simulation time 252070737000 ps
CPU time 5479.66 seconds
Started Mar 24 02:00:40 PM PDT 24
Finished Mar 24 03:32:01 PM PDT 24
Peak memory 647156 kb
Host smart-4f6688b5-2443-4e37-bc59-455cf06535fd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2338574888 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_128.2338574888 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/19.kmac_test_vectors_shake_256.4160193094
Short name T345
Test name
Test status
Simulation time 390353561713 ps
CPU time 5085.99 seconds
Started Mar 24 02:00:44 PM PDT 24
Finished Mar 24 03:25:31 PM PDT 24
Peak memory 587948 kb
Host smart-2a4115d8-3f05-4f6f-aa98-d54b77a30356
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4160193094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_test_vectors_shake_256.4160193094 +enable_masking=1 +sw_key_masked=0
Directory /workspace/19.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/2.kmac_alert_test.2545834319
Short name T1044
Test name
Test status
Simulation time 14058027 ps
CPU time 0.82 seconds
Started Mar 24 01:57:45 PM PDT 24
Finished Mar 24 01:57:46 PM PDT 24
Peak memory 218460 kb
Host smart-29bba4e6-8599-4018-8aca-1166c1c70dc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545834319 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.2545834319 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_alert_test/latest

Test location /workspace/coverage/default/2.kmac_app.1187557451
Short name T324
Test name
Test status
Simulation time 160653412437 ps
CPU time 277.29 seconds
Started Mar 24 01:57:54 PM PDT 24
Finished Mar 24 02:02:31 PM PDT 24
Peak memory 244956 kb
Host smart-b34cec55-3dcc-4f96-ac83-bc3cc46ad873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187557451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.1187557451 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app/latest

Test location /workspace/coverage/default/2.kmac_app_with_partial_data.1034495155
Short name T894
Test name
Test status
Simulation time 1444718878 ps
CPU time 20.33 seconds
Started Mar 24 01:57:43 PM PDT 24
Finished Mar 24 01:58:04 PM PDT 24
Peak memory 221840 kb
Host smart-a1b8c571-41fa-4870-bd89-603989676011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034495155 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.1034495155 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/2.kmac_burst_write.3488953914
Short name T133
Test name
Test status
Simulation time 12003775715 ps
CPU time 1303.84 seconds
Started Mar 24 01:57:40 PM PDT 24
Finished Mar 24 02:19:24 PM PDT 24
Peak memory 243208 kb
Host smart-05bb3726-212b-42b8-9aa1-a36fc6abc8f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488953914 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.3488953914 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_burst_write/latest

Test location /workspace/coverage/default/2.kmac_edn_timeout_error.2929476136
Short name T272
Test name
Test status
Simulation time 81272590 ps
CPU time 1.21 seconds
Started Mar 24 01:57:43 PM PDT 24
Finished Mar 24 01:57:44 PM PDT 24
Peak memory 218588 kb
Host smart-5682613c-dc54-4fcb-ae76-c34d144c69dc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2929476136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.2929476136 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_mode_error.3493599668
Short name T707
Test name
Test status
Simulation time 62930724 ps
CPU time 0.92 seconds
Started Mar 24 01:57:47 PM PDT 24
Finished Mar 24 01:57:48 PM PDT 24
Peak memory 220800 kb
Host smart-643ebed4-36e5-4d98-9f15-253b42ab6a76
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3493599668 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.3493599668 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/2.kmac_entropy_ready_error.2705259905
Short name T859
Test name
Test status
Simulation time 6138967388 ps
CPU time 24.07 seconds
Started Mar 24 01:57:48 PM PDT 24
Finished Mar 24 01:58:12 PM PDT 24
Peak memory 226844 kb
Host smart-08213699-c706-4d66-ac25-4067829c64d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705259905 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.2705259905 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/2.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/2.kmac_error.2030406520
Short name T993
Test name
Test status
Simulation time 9797755516 ps
CPU time 216.28 seconds
Started Mar 24 01:57:44 PM PDT 24
Finished Mar 24 02:01:20 PM PDT 24
Peak memory 259520 kb
Host smart-c7399c89-2328-471e-9105-c63e06c0fe39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030406520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.2030406520 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_error/latest

Test location /workspace/coverage/default/2.kmac_key_error.3019392236
Short name T699
Test name
Test status
Simulation time 168211898 ps
CPU time 1.65 seconds
Started Mar 24 01:57:41 PM PDT 24
Finished Mar 24 01:57:43 PM PDT 24
Peak memory 218556 kb
Host smart-52bdb92a-2dcb-4beb-95bb-d6858d57f645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019392236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.3019392236 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_key_error/latest

Test location /workspace/coverage/default/2.kmac_long_msg_and_output.4242023588
Short name T923
Test name
Test status
Simulation time 236277825240 ps
CPU time 2121.69 seconds
Started Mar 24 01:57:42 PM PDT 24
Finished Mar 24 02:33:04 PM PDT 24
Peak memory 391816 kb
Host smart-f9dff476-7fee-408a-851a-071af457e8cc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242023588 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_an
d_output.4242023588 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/2.kmac_mubi.424820482
Short name T42
Test name
Test status
Simulation time 62773440384 ps
CPU time 363.81 seconds
Started Mar 24 01:57:42 PM PDT 24
Finished Mar 24 02:03:46 PM PDT 24
Peak memory 250676 kb
Host smart-579f13d1-ea48-4281-a624-effaf23906b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424820482 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.424820482 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_mubi/latest

Test location /workspace/coverage/default/2.kmac_sec_cm.4038892998
Short name T31
Test name
Test status
Simulation time 27912591460 ps
CPU time 118.68 seconds
Started Mar 24 01:57:59 PM PDT 24
Finished Mar 24 01:59:57 PM PDT 24
Peak memory 298048 kb
Host smart-55545600-b600-44e6-8188-5a41e1fa8eec
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038892998 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.4038892998 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/2.kmac_sec_cm/latest

Test location /workspace/coverage/default/2.kmac_sideload.3758339427
Short name T919
Test name
Test status
Simulation time 73983469207 ps
CPU time 361.23 seconds
Started Mar 24 01:57:43 PM PDT 24
Finished Mar 24 02:03:44 PM PDT 24
Peak memory 248452 kb
Host smart-abbd17b9-97ca-4238-beb6-141539b348db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3758339427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.3758339427 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_sideload/latest

Test location /workspace/coverage/default/2.kmac_smoke.2886578151
Short name T908
Test name
Test status
Simulation time 753099403 ps
CPU time 20.14 seconds
Started Mar 24 01:57:43 PM PDT 24
Finished Mar 24 01:58:03 PM PDT 24
Peak memory 222800 kb
Host smart-f767c219-f0a4-4b72-b224-959562af7a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886578151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.2886578151 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_smoke/latest

Test location /workspace/coverage/default/2.kmac_stress_all.2858686827
Short name T8
Test name
Test status
Simulation time 112249211047 ps
CPU time 3036.69 seconds
Started Mar 24 01:57:59 PM PDT 24
Finished Mar 24 02:48:36 PM PDT 24
Peak memory 451936 kb
Host smart-e537c81e-d64c-4d9c-8fcc-e7f6d803b2b0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2858686827 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all.2858686827 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_stress_all/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac.738242112
Short name T357
Test name
Test status
Simulation time 1552773260 ps
CPU time 7.42 seconds
Started Mar 24 01:57:45 PM PDT 24
Finished Mar 24 01:57:53 PM PDT 24
Peak memory 218572 kb
Host smart-56fe651d-9053-4190-a99e-ec99b88e6f28
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738242112 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 2.kmac_test_vectors_kmac.738242112 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_kmac_xof.1628214614
Short name T537
Test name
Test status
Simulation time 352896679 ps
CPU time 6.37 seconds
Started Mar 24 01:57:44 PM PDT 24
Finished Mar 24 01:57:50 PM PDT 24
Peak memory 218644 kb
Host smart-967eab75-3fc8-4631-970d-6ccee7a79064
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628214614 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 2.kmac_test_vectors_kmac_xof.1628214614 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_224.562531098
Short name T961
Test name
Test status
Simulation time 99981645978 ps
CPU time 2406.88 seconds
Started Mar 24 01:57:42 PM PDT 24
Finished Mar 24 02:37:49 PM PDT 24
Peak memory 388528 kb
Host smart-32eb68ea-2b4a-427a-9ed0-ab5ded03bc16
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=562531098 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.562531098 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_256.3927991246
Short name T695
Test name
Test status
Simulation time 80704836984 ps
CPU time 1947.1 seconds
Started Mar 24 01:57:44 PM PDT 24
Finished Mar 24 02:30:12 PM PDT 24
Peak memory 391960 kb
Host smart-0801f7ec-8f0c-4333-9048-4c91fa5229ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3927991246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.3927991246 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_384.4126115801
Short name T200
Test name
Test status
Simulation time 223829223926 ps
CPU time 1559.33 seconds
Started Mar 24 01:57:46 PM PDT 24
Finished Mar 24 02:23:46 PM PDT 24
Peak memory 336260 kb
Host smart-8e67b6ff-2690-44f7-9135-6a88ff56669d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4126115801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.4126115801 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_sha3_512.1866186622
Short name T564
Test name
Test status
Simulation time 198355807138 ps
CPU time 1327.79 seconds
Started Mar 24 01:57:42 PM PDT 24
Finished Mar 24 02:19:50 PM PDT 24
Peak memory 303680 kb
Host smart-9ccc4f94-5f54-428f-aed7-3913bc98617a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1866186622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.1866186622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_128.3202399545
Short name T412
Test name
Test status
Simulation time 260842561369 ps
CPU time 5877.56 seconds
Started Mar 24 01:57:44 PM PDT 24
Finished Mar 24 03:35:43 PM PDT 24
Peak memory 656356 kb
Host smart-54c5f270-e223-41fe-8252-a47b9360dc7e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3202399545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3202399545 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/2.kmac_test_vectors_shake_256.465151476
Short name T344
Test name
Test status
Simulation time 797374475554 ps
CPU time 5130.89 seconds
Started Mar 24 01:57:43 PM PDT 24
Finished Mar 24 03:23:15 PM PDT 24
Peak memory 572616 kb
Host smart-f4d4f7fb-6e46-4672-8687-581e2ee993e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=465151476 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.465151476 +enable_masking=1 +sw_key_masked=0
Directory /workspace/2.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/20.kmac_alert_test.1763488946
Short name T3
Test name
Test status
Simulation time 49005978 ps
CPU time 0.8 seconds
Started Mar 24 02:01:07 PM PDT 24
Finished Mar 24 02:01:07 PM PDT 24
Peak memory 218488 kb
Host smart-5ea93e6c-8ebc-4861-a693-faef0116f039
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763488946 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_alert_test.1763488946 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_alert_test/latest

Test location /workspace/coverage/default/20.kmac_app.3713444451
Short name T842
Test name
Test status
Simulation time 153423610 ps
CPU time 3.92 seconds
Started Mar 24 02:00:58 PM PDT 24
Finished Mar 24 02:01:02 PM PDT 24
Peak memory 221872 kb
Host smart-121436ad-4d88-4d29-b2cb-9f3c76db9028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713444451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.3713444451 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_app/latest

Test location /workspace/coverage/default/20.kmac_burst_write.3991659129
Short name T343
Test name
Test status
Simulation time 5911144989 ps
CPU time 639.6 seconds
Started Mar 24 02:00:53 PM PDT 24
Finished Mar 24 02:11:33 PM PDT 24
Peak memory 232568 kb
Host smart-9db308c9-30af-43eb-8484-fb09fd5b326b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991659129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_burst_write.3991659129 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_burst_write/latest

Test location /workspace/coverage/default/20.kmac_entropy_refresh.402478551
Short name T47
Test name
Test status
Simulation time 68605882364 ps
CPU time 404.95 seconds
Started Mar 24 02:00:59 PM PDT 24
Finished Mar 24 02:07:44 PM PDT 24
Peak memory 250780 kb
Host smart-7d292429-fea6-4d6a-8520-2ca6561fd7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402478551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_entropy_refresh.402478551 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/20.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/20.kmac_error.2849980899
Short name T453
Test name
Test status
Simulation time 11211209188 ps
CPU time 354.53 seconds
Started Mar 24 02:01:04 PM PDT 24
Finished Mar 24 02:06:59 PM PDT 24
Peak memory 259436 kb
Host smart-7c9e2e2a-e07a-4728-837e-25e687e711a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849980899 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_error.2849980899 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_error/latest

Test location /workspace/coverage/default/20.kmac_key_error.3466123575
Short name T540
Test name
Test status
Simulation time 601566211 ps
CPU time 2.49 seconds
Started Mar 24 02:01:05 PM PDT 24
Finished Mar 24 02:01:08 PM PDT 24
Peak memory 218532 kb
Host smart-85a36233-2d82-4a78-a776-f89212be83b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466123575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_key_error.3466123575 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_key_error/latest

Test location /workspace/coverage/default/20.kmac_lc_escalation.654664271
Short name T988
Test name
Test status
Simulation time 278276900 ps
CPU time 1.39 seconds
Started Mar 24 02:01:02 PM PDT 24
Finished Mar 24 02:01:04 PM PDT 24
Peak memory 218672 kb
Host smart-59627d95-0403-4308-b531-f87ba7e1d486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654664271 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.654664271 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/20.kmac_lc_escalation/latest

Test location /workspace/coverage/default/20.kmac_long_msg_and_output.1341393198
Short name T895
Test name
Test status
Simulation time 12935487895 ps
CPU time 304.68 seconds
Started Mar 24 02:00:54 PM PDT 24
Finished Mar 24 02:05:59 PM PDT 24
Peak memory 251440 kb
Host smart-e8f90686-6b71-428c-b176-ed5697440e17
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341393198 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_long_msg_a
nd_output.1341393198 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/20.kmac_sideload.799534990
Short name T1074
Test name
Test status
Simulation time 77996620767 ps
CPU time 525.42 seconds
Started Mar 24 02:00:54 PM PDT 24
Finished Mar 24 02:09:39 PM PDT 24
Peak memory 255300 kb
Host smart-14faf093-6044-4c28-9625-8b8dac6a2acb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799534990 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload.799534990 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_sideload/latest

Test location /workspace/coverage/default/20.kmac_smoke.2066313088
Short name T603
Test name
Test status
Simulation time 1775828478 ps
CPU time 8.69 seconds
Started Mar 24 02:00:52 PM PDT 24
Finished Mar 24 02:01:01 PM PDT 24
Peak memory 225476 kb
Host smart-3b38f323-0ca2-4d0a-ad69-305446bd4d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066313088 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_smoke.2066313088 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_smoke/latest

Test location /workspace/coverage/default/20.kmac_stress_all.2920991725
Short name T692
Test name
Test status
Simulation time 229424970645 ps
CPU time 1233.31 seconds
Started Mar 24 02:01:04 PM PDT 24
Finished Mar 24 02:21:37 PM PDT 24
Peak memory 338352 kb
Host smart-67b44283-b583-4f74-9fe7-b502019a37e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2920991725 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all.2920991725 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all/latest

Test location /workspace/coverage/default/20.kmac_stress_all_with_rand_reset.198904557
Short name T39
Test name
Test status
Simulation time 133043318547 ps
CPU time 1646.83 seconds
Started Mar 24 02:01:03 PM PDT 24
Finished Mar 24 02:28:30 PM PDT 24
Peak memory 357368 kb
Host smart-51fe343b-e8d8-4f2d-bace-6cd801f648ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=198904557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_stress_all_with_rand_reset.198904557 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac.896871574
Short name T365
Test name
Test status
Simulation time 2658685960 ps
CPU time 6.47 seconds
Started Mar 24 02:00:59 PM PDT 24
Finished Mar 24 02:01:05 PM PDT 24
Peak memory 226788 kb
Host smart-1b88cd7d-bf11-4413-80bb-6d14c9b7ea66
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896871574 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 20.kmac_test_vectors_kmac.896871574 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_kmac_xof.812194530
Short name T860
Test name
Test status
Simulation time 478034449 ps
CPU time 6.94 seconds
Started Mar 24 02:00:59 PM PDT 24
Finished Mar 24 02:01:06 PM PDT 24
Peak memory 226988 kb
Host smart-c17d3cb8-6357-4e2d-ae62-c333c0fb94a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812194530 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 20.kmac_test_vectors_kmac_xof.812194530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_224.1191521570
Short name T1050
Test name
Test status
Simulation time 284238732491 ps
CPU time 2344.9 seconds
Started Mar 24 02:00:53 PM PDT 24
Finished Mar 24 02:39:58 PM PDT 24
Peak memory 396848 kb
Host smart-84c3dc42-47d1-404a-b258-f44bce6a1fc0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1191521570 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_224.1191521570 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_256.3754183133
Short name T1017
Test name
Test status
Simulation time 126827582574 ps
CPU time 1978.67 seconds
Started Mar 24 02:00:53 PM PDT 24
Finished Mar 24 02:33:52 PM PDT 24
Peak memory 379644 kb
Host smart-8299d2b6-88e7-4e7a-8124-dfad589a67fb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3754183133 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_256.3754183133 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_384.4112860928
Short name T765
Test name
Test status
Simulation time 209417403942 ps
CPU time 1733.94 seconds
Started Mar 24 02:00:53 PM PDT 24
Finished Mar 24 02:29:48 PM PDT 24
Peak memory 343696 kb
Host smart-874c8096-7a25-4117-9454-1d4fe976541b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4112860928 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_384.4112860928 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_sha3_512.983285164
Short name T1059
Test name
Test status
Simulation time 21195170496 ps
CPU time 1168.22 seconds
Started Mar 24 02:00:53 PM PDT 24
Finished Mar 24 02:20:22 PM PDT 24
Peak memory 302140 kb
Host smart-4cb78a5c-f680-442a-ab89-1878e2d5a205
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=983285164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_sha3_512.983285164 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_128.186091879
Short name T483
Test name
Test status
Simulation time 59724030407 ps
CPU time 4809.33 seconds
Started Mar 24 02:00:58 PM PDT 24
Finished Mar 24 03:21:08 PM PDT 24
Peak memory 646364 kb
Host smart-563034ad-6a70-474f-b11a-fdb3803bb1ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=186091879 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_128.186091879 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/20.kmac_test_vectors_shake_256.875476691
Short name T373
Test name
Test status
Simulation time 221887033246 ps
CPU time 5158.55 seconds
Started Mar 24 02:00:59 PM PDT 24
Finished Mar 24 03:26:58 PM PDT 24
Peak memory 562952 kb
Host smart-5fd4976c-c50a-421b-ab1b-ff498c9afd65
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=875476691 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_test_vectors_shake_256.875476691 +enable_masking=1 +sw_key_masked=0
Directory /workspace/20.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/21.kmac_alert_test.1296621671
Short name T2
Test name
Test status
Simulation time 49578216 ps
CPU time 0.88 seconds
Started Mar 24 02:01:27 PM PDT 24
Finished Mar 24 02:01:28 PM PDT 24
Peak memory 218476 kb
Host smart-34c2c804-f973-42b0-b4e3-c1cf82f182f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1296621671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_alert_test.1296621671 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_alert_test/latest

Test location /workspace/coverage/default/21.kmac_burst_write.3840990241
Short name T322
Test name
Test status
Simulation time 11831366438 ps
CPU time 343.48 seconds
Started Mar 24 02:01:08 PM PDT 24
Finished Mar 24 02:06:52 PM PDT 24
Peak memory 231248 kb
Host smart-807b441a-3efe-4a8b-9619-f84164472442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840990241 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_burst_write.3840990241 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_burst_write/latest

Test location /workspace/coverage/default/21.kmac_entropy_refresh.633900917
Short name T46
Test name
Test status
Simulation time 122506395954 ps
CPU time 386.45 seconds
Started Mar 24 02:01:15 PM PDT 24
Finished Mar 24 02:07:42 PM PDT 24
Peak memory 249368 kb
Host smart-6bfec531-86b3-40b9-8855-79aec0e9952d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633900917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_entropy_refresh.633900917 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/21.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/21.kmac_error.219501413
Short name T270
Test name
Test status
Simulation time 16043368764 ps
CPU time 482.41 seconds
Started Mar 24 02:01:21 PM PDT 24
Finished Mar 24 02:09:24 PM PDT 24
Peak memory 259520 kb
Host smart-6cfbc797-4cb9-4b24-9dd9-772db696986a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219501413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_error.219501413 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_error/latest

Test location /workspace/coverage/default/21.kmac_key_error.4168770584
Short name T54
Test name
Test status
Simulation time 1501933542 ps
CPU time 2.67 seconds
Started Mar 24 02:01:21 PM PDT 24
Finished Mar 24 02:01:24 PM PDT 24
Peak memory 218520 kb
Host smart-07e3efb0-3129-4240-a3e7-daf0754c2a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168770584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_key_error.4168770584 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_key_error/latest

Test location /workspace/coverage/default/21.kmac_lc_escalation.1528870599
Short name T12
Test name
Test status
Simulation time 71760809 ps
CPU time 1.37 seconds
Started Mar 24 02:01:22 PM PDT 24
Finished Mar 24 02:01:23 PM PDT 24
Peak memory 218636 kb
Host smart-2b6816ee-79ce-490d-9a4b-85aeb85379e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528870599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.1528870599 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/21.kmac_lc_escalation/latest

Test location /workspace/coverage/default/21.kmac_long_msg_and_output.4148747258
Short name T463
Test name
Test status
Simulation time 40695600833 ps
CPU time 1574.82 seconds
Started Mar 24 02:01:07 PM PDT 24
Finished Mar 24 02:27:22 PM PDT 24
Peak memory 336440 kb
Host smart-bc803886-1641-47cf-82ca-0d0550393d83
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148747258 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_long_msg_a
nd_output.4148747258 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/21.kmac_sideload.2091124618
Short name T419
Test name
Test status
Simulation time 21009647578 ps
CPU time 542.68 seconds
Started Mar 24 02:01:07 PM PDT 24
Finished Mar 24 02:10:10 PM PDT 24
Peak memory 258016 kb
Host smart-5a56b355-f1c3-4725-9648-5ba34ba330d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091124618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload.2091124618 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_sideload/latest

Test location /workspace/coverage/default/21.kmac_smoke.2987238147
Short name T229
Test name
Test status
Simulation time 2409267858 ps
CPU time 24.35 seconds
Started Mar 24 02:01:07 PM PDT 24
Finished Mar 24 02:01:31 PM PDT 24
Peak memory 226812 kb
Host smart-df64ea61-1684-4ea2-981e-6e4ff3ad8561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987238147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_smoke.2987238147 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_smoke/latest

Test location /workspace/coverage/default/21.kmac_stress_all.104945468
Short name T957
Test name
Test status
Simulation time 33834897158 ps
CPU time 406.3 seconds
Started Mar 24 02:01:21 PM PDT 24
Finished Mar 24 02:08:07 PM PDT 24
Peak memory 270092 kb
Host smart-80da0fe3-f973-4bfc-a557-677c9f0edbb9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=104945468 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all.104945468 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all/latest

Test location /workspace/coverage/default/21.kmac_stress_all_with_rand_reset.3360917509
Short name T575
Test name
Test status
Simulation time 116248777939 ps
CPU time 909.24 seconds
Started Mar 24 02:01:25 PM PDT 24
Finished Mar 24 02:16:35 PM PDT 24
Peak memory 276268 kb
Host smart-4ed837c4-d5f4-44d8-93e1-859933d982a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3360917509 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_stress_all_with_rand_reset.3360917509 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac.1330276604
Short name T925
Test name
Test status
Simulation time 416856279 ps
CPU time 6.04 seconds
Started Mar 24 02:01:12 PM PDT 24
Finished Mar 24 02:01:18 PM PDT 24
Peak memory 218672 kb
Host smart-9c972c86-a95f-432a-98e8-46e00b0e52d1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330276604 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 21.kmac_test_vectors_kmac.1330276604 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_kmac_xof.746774848
Short name T833
Test name
Test status
Simulation time 196783005 ps
CPU time 5.67 seconds
Started Mar 24 02:01:10 PM PDT 24
Finished Mar 24 02:01:16 PM PDT 24
Peak memory 218608 kb
Host smart-fdb511d0-cbfd-45c2-8f87-79efcb17b401
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746774848 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 21.kmac_test_vectors_kmac_xof.746774848 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_224.1964080172
Short name T472
Test name
Test status
Simulation time 21199131132 ps
CPU time 2063.9 seconds
Started Mar 24 02:01:09 PM PDT 24
Finished Mar 24 02:35:33 PM PDT 24
Peak memory 397304 kb
Host smart-7ee61112-48c0-46e7-9338-a3dfa6919acb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1964080172 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_224.1964080172 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_256.2896532603
Short name T747
Test name
Test status
Simulation time 79158983399 ps
CPU time 1857.63 seconds
Started Mar 24 02:01:12 PM PDT 24
Finished Mar 24 02:32:10 PM PDT 24
Peak memory 376988 kb
Host smart-fdaedbd6-09c4-469e-ad4e-a7387186d8cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2896532603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_256.2896532603 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_384.3937060087
Short name T487
Test name
Test status
Simulation time 690007835182 ps
CPU time 1527.43 seconds
Started Mar 24 02:01:16 PM PDT 24
Finished Mar 24 02:26:44 PM PDT 24
Peak memory 342768 kb
Host smart-a3c2c7cb-ce1d-4e6d-a6ec-105f715dd00c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3937060087 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_384.3937060087 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_sha3_512.2638640641
Short name T744
Test name
Test status
Simulation time 93797924318 ps
CPU time 1294.98 seconds
Started Mar 24 02:01:10 PM PDT 24
Finished Mar 24 02:22:45 PM PDT 24
Peak memory 296808 kb
Host smart-9857e060-0254-40ea-88d4-6d6a42883256
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2638640641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_sha3_512.2638640641 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_128.500462351
Short name T233
Test name
Test status
Simulation time 1079906995372 ps
CPU time 6658.2 seconds
Started Mar 24 02:01:12 PM PDT 24
Finished Mar 24 03:52:11 PM PDT 24
Peak memory 659516 kb
Host smart-018e3bcf-ea45-45df-ae62-d0bbd880968e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=500462351 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_128.500462351 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/21.kmac_test_vectors_shake_256.3743708582
Short name T705
Test name
Test status
Simulation time 101848443481 ps
CPU time 4481.24 seconds
Started Mar 24 02:01:11 PM PDT 24
Finished Mar 24 03:15:53 PM PDT 24
Peak memory 582332 kb
Host smart-48b02dd0-30ac-46c3-85f6-3404f41c6cde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3743708582 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_test_vectors_shake_256.3743708582 +enable_masking=1 +sw_key_masked=0
Directory /workspace/21.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/22.kmac_alert_test.2544660599
Short name T268
Test name
Test status
Simulation time 28828645 ps
CPU time 0.8 seconds
Started Mar 24 02:01:41 PM PDT 24
Finished Mar 24 02:01:42 PM PDT 24
Peak memory 218748 kb
Host smart-a080bc93-70e5-42b4-920a-ab80c28fe816
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2544660599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_alert_test.2544660599 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_alert_test/latest

Test location /workspace/coverage/default/22.kmac_app.628462747
Short name T226
Test name
Test status
Simulation time 69181381209 ps
CPU time 132.99 seconds
Started Mar 24 02:01:35 PM PDT 24
Finished Mar 24 02:03:48 PM PDT 24
Peak memory 238172 kb
Host smart-bb74c687-657d-4ec8-8ce2-376887b8f140
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628462747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.628462747 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_app/latest

Test location /workspace/coverage/default/22.kmac_burst_write.154006467
Short name T858
Test name
Test status
Simulation time 24925510711 ps
CPU time 704.08 seconds
Started Mar 24 02:01:26 PM PDT 24
Finished Mar 24 02:13:11 PM PDT 24
Peak memory 234924 kb
Host smart-afefe9b7-f230-46a6-b7f6-66c73c9005d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154006467 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_burst_write.154006467 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_burst_write/latest

Test location /workspace/coverage/default/22.kmac_entropy_refresh.1928912732
Short name T449
Test name
Test status
Simulation time 56982661157 ps
CPU time 334.24 seconds
Started Mar 24 02:01:36 PM PDT 24
Finished Mar 24 02:07:10 PM PDT 24
Peak memory 246628 kb
Host smart-605e550c-911f-42f0-b6ed-a3cccc00d1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928912732 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_entropy_refresh.1928912732 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/22.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/22.kmac_error.3216355676
Short name T477
Test name
Test status
Simulation time 2397600752 ps
CPU time 192.86 seconds
Started Mar 24 02:01:44 PM PDT 24
Finished Mar 24 02:04:57 PM PDT 24
Peak memory 258836 kb
Host smart-676db41e-7885-4125-817f-df6487722e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216355676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_error.3216355676 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_error/latest

Test location /workspace/coverage/default/22.kmac_key_error.1083418684
Short name T467
Test name
Test status
Simulation time 3450426302 ps
CPU time 5.2 seconds
Started Mar 24 02:01:42 PM PDT 24
Finished Mar 24 02:01:48 PM PDT 24
Peak memory 218592 kb
Host smart-6fe18fdf-3c71-4060-bd92-c82f0d0654d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083418684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_key_error.1083418684 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_key_error/latest

Test location /workspace/coverage/default/22.kmac_long_msg_and_output.3171543353
Short name T904
Test name
Test status
Simulation time 39749853770 ps
CPU time 556.39 seconds
Started Mar 24 02:01:25 PM PDT 24
Finished Mar 24 02:10:41 PM PDT 24
Peak memory 264676 kb
Host smart-719ecee7-aab4-419d-a63e-8a23d893846c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171543353 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_long_msg_a
nd_output.3171543353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/22.kmac_sideload.1459625210
Short name T758
Test name
Test status
Simulation time 13981722015 ps
CPU time 500.92 seconds
Started Mar 24 02:01:26 PM PDT 24
Finished Mar 24 02:09:47 PM PDT 24
Peak memory 256152 kb
Host smart-13c2e50b-c661-4ff6-b443-09a4c222e6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459625210 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload.1459625210 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_sideload/latest

Test location /workspace/coverage/default/22.kmac_smoke.49783794
Short name T784
Test name
Test status
Simulation time 94818748 ps
CPU time 2.88 seconds
Started Mar 24 02:01:26 PM PDT 24
Finished Mar 24 02:01:29 PM PDT 24
Peak memory 223308 kb
Host smart-21985724-5e97-447e-b0fb-0b7a8bf5bf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49783794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_smoke.49783794 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_smoke/latest

Test location /workspace/coverage/default/22.kmac_stress_all.3300949848
Short name T597
Test name
Test status
Simulation time 20095903082 ps
CPU time 1746.27 seconds
Started Mar 24 02:01:42 PM PDT 24
Finished Mar 24 02:30:48 PM PDT 24
Peak memory 399752 kb
Host smart-cbd77894-fdc5-4d5d-a122-c35a25360799
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3300949848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_stress_all.3300949848 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_stress_all/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac.3590350789
Short name T554
Test name
Test status
Simulation time 145056587 ps
CPU time 5.51 seconds
Started Mar 24 02:01:30 PM PDT 24
Finished Mar 24 02:01:36 PM PDT 24
Peak memory 219624 kb
Host smart-5312798f-61bc-47e0-b426-38b1a2b5f683
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590350789 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 22.kmac_test_vectors_kmac.3590350789 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_kmac_xof.1287206591
Short name T1065
Test name
Test status
Simulation time 889210706 ps
CPU time 6.9 seconds
Started Mar 24 02:01:35 PM PDT 24
Finished Mar 24 02:01:42 PM PDT 24
Peak memory 226664 kb
Host smart-75ecd7ff-ba37-4152-ada6-96dde060e9a8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287206591 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 22.kmac_test_vectors_kmac_xof.1287206591 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_224.1865545328
Short name T623
Test name
Test status
Simulation time 579080983904 ps
CPU time 2613.22 seconds
Started Mar 24 02:01:28 PM PDT 24
Finished Mar 24 02:45:01 PM PDT 24
Peak memory 402048 kb
Host smart-bff9558f-f41f-4018-8a82-c781d42e5301
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1865545328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_224.1865545328 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_256.3879948572
Short name T572
Test name
Test status
Simulation time 22201791802 ps
CPU time 1846.08 seconds
Started Mar 24 02:01:28 PM PDT 24
Finished Mar 24 02:32:14 PM PDT 24
Peak memory 389372 kb
Host smart-eb6e8c4c-5ccd-441d-bfc6-fbee470242ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3879948572 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_256.3879948572 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_384.4078331777
Short name T328
Test name
Test status
Simulation time 72448386927 ps
CPU time 1871.12 seconds
Started Mar 24 02:01:27 PM PDT 24
Finished Mar 24 02:32:38 PM PDT 24
Peak memory 339360 kb
Host smart-4784e870-fbd5-403a-a33a-747d625863ea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4078331777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_384.4078331777 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_sha3_512.541467221
Short name T673
Test name
Test status
Simulation time 237297307505 ps
CPU time 1238.39 seconds
Started Mar 24 02:01:28 PM PDT 24
Finished Mar 24 02:22:07 PM PDT 24
Peak memory 302896 kb
Host smart-c136fee3-9902-4ff1-ad98-406dac2361f3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=541467221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_sha3_512.541467221 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_128.1795984454
Short name T499
Test name
Test status
Simulation time 191224091378 ps
CPU time 5610.06 seconds
Started Mar 24 02:01:31 PM PDT 24
Finished Mar 24 03:35:01 PM PDT 24
Peak memory 673100 kb
Host smart-88d00d69-b5e6-452c-8371-20b2c2f176da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1795984454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_128.1795984454 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/22.kmac_test_vectors_shake_256.1862813515
Short name T462
Test name
Test status
Simulation time 587038684211 ps
CPU time 4428.77 seconds
Started Mar 24 02:01:30 PM PDT 24
Finished Mar 24 03:15:19 PM PDT 24
Peak memory 574424 kb
Host smart-f6269fe9-a874-43ae-9330-ff209fc08226
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1862813515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_test_vectors_shake_256.1862813515 +enable_masking=1 +sw_key_masked=0
Directory /workspace/22.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/23.kmac_alert_test.1070889441
Short name T514
Test name
Test status
Simulation time 15117088 ps
CPU time 0.84 seconds
Started Mar 24 02:01:57 PM PDT 24
Finished Mar 24 02:01:58 PM PDT 24
Peak memory 220576 kb
Host smart-3b787dec-a725-4e84-8169-6f4b8bdfbdff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070889441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_alert_test.1070889441 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_alert_test/latest

Test location /workspace/coverage/default/23.kmac_app.906775773
Short name T414
Test name
Test status
Simulation time 35261315817 ps
CPU time 286.58 seconds
Started Mar 24 02:01:58 PM PDT 24
Finished Mar 24 02:06:44 PM PDT 24
Peak memory 245672 kb
Host smart-d6a77be5-32d1-41c7-a195-37c2323d0012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906775773 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.906775773 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_app/latest

Test location /workspace/coverage/default/23.kmac_burst_write.802254383
Short name T251
Test name
Test status
Simulation time 7974189489 ps
CPU time 713.92 seconds
Started Mar 24 02:01:47 PM PDT 24
Finished Mar 24 02:13:41 PM PDT 24
Peak memory 235848 kb
Host smart-c0b8669f-1f79-4378-9ce6-5bebb9cda43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802254383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_burst_write.802254383 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_burst_write/latest

Test location /workspace/coverage/default/23.kmac_entropy_refresh.721165329
Short name T926
Test name
Test status
Simulation time 6137698788 ps
CPU time 50.05 seconds
Started Mar 24 02:02:01 PM PDT 24
Finished Mar 24 02:02:51 PM PDT 24
Peak memory 227808 kb
Host smart-f5bb3501-570a-4541-bfcd-928101f41012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721165329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_entropy_refresh.721165329 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/23.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/23.kmac_error.3303724230
Short name T739
Test name
Test status
Simulation time 50598569439 ps
CPU time 489.94 seconds
Started Mar 24 02:01:58 PM PDT 24
Finished Mar 24 02:10:08 PM PDT 24
Peak memory 259760 kb
Host smart-cf2ba474-89f1-43eb-b79f-76a32ef33bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303724230 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_error.3303724230 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_error/latest

Test location /workspace/coverage/default/23.kmac_key_error.254830272
Short name T49
Test name
Test status
Simulation time 4356520720 ps
CPU time 6.61 seconds
Started Mar 24 02:01:57 PM PDT 24
Finished Mar 24 02:02:03 PM PDT 24
Peak memory 218532 kb
Host smart-6c5cbacf-2d43-4a10-a31f-4891a8c0e573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254830272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_key_error.254830272 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_key_error/latest

Test location /workspace/coverage/default/23.kmac_lc_escalation.228287913
Short name T821
Test name
Test status
Simulation time 55625048 ps
CPU time 1.35 seconds
Started Mar 24 02:01:57 PM PDT 24
Finished Mar 24 02:01:59 PM PDT 24
Peak memory 218616 kb
Host smart-6598f31e-14dd-4ebb-9562-0255ce8bc46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228287913 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.228287913 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/23.kmac_lc_escalation/latest

Test location /workspace/coverage/default/23.kmac_long_msg_and_output.284401973
Short name T182
Test name
Test status
Simulation time 52651224670 ps
CPU time 1914.3 seconds
Started Mar 24 02:01:46 PM PDT 24
Finished Mar 24 02:33:40 PM PDT 24
Peak memory 379928 kb
Host smart-26494005-91f8-4093-a7dd-c0839c556e98
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284401973 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_long_msg_an
d_output.284401973 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/23.kmac_sideload.2253981617
Short name T203
Test name
Test status
Simulation time 20179084449 ps
CPU time 513.46 seconds
Started Mar 24 02:01:45 PM PDT 24
Finished Mar 24 02:10:19 PM PDT 24
Peak memory 255604 kb
Host smart-a052a043-7e5f-478f-85d2-49aaf6d07e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253981617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload.2253981617 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_sideload/latest

Test location /workspace/coverage/default/23.kmac_smoke.1439693809
Short name T375
Test name
Test status
Simulation time 9806596646 ps
CPU time 63.11 seconds
Started Mar 24 02:01:42 PM PDT 24
Finished Mar 24 02:02:45 PM PDT 24
Peak memory 226784 kb
Host smart-0262f71b-7e4e-46d7-9d9d-71e2507dd019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439693809 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_smoke.1439693809 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_smoke/latest

Test location /workspace/coverage/default/23.kmac_stress_all.1066593677
Short name T1045
Test name
Test status
Simulation time 21271536901 ps
CPU time 707.27 seconds
Started Mar 24 02:01:57 PM PDT 24
Finished Mar 24 02:13:45 PM PDT 24
Peak memory 300492 kb
Host smart-1a75acaa-2187-4d47-b497-daaee11a98f5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1066593677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_stress_all.1066593677 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_stress_all/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac.1413985619
Short name T235
Test name
Test status
Simulation time 554585605 ps
CPU time 6.95 seconds
Started Mar 24 02:01:59 PM PDT 24
Finished Mar 24 02:02:06 PM PDT 24
Peak memory 226692 kb
Host smart-944cd293-b9fc-461f-ba27-636d15a4c29a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413985619 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 23.kmac_test_vectors_kmac.1413985619 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_kmac_xof.1380681417
Short name T282
Test name
Test status
Simulation time 1633604861 ps
CPU time 6.38 seconds
Started Mar 24 02:01:57 PM PDT 24
Finished Mar 24 02:02:04 PM PDT 24
Peak memory 218656 kb
Host smart-5c8e01e9-9331-496a-88d7-b10dd1630ac9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380681417 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 23.kmac_test_vectors_kmac_xof.1380681417 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_224.4002890955
Short name T962
Test name
Test status
Simulation time 288451845784 ps
CPU time 2257.58 seconds
Started Mar 24 02:01:47 PM PDT 24
Finished Mar 24 02:39:25 PM PDT 24
Peak memory 400716 kb
Host smart-56cbefe5-0997-4899-b264-6e141f8df444
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4002890955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_224.4002890955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_256.3680873518
Short name T196
Test name
Test status
Simulation time 40524339496 ps
CPU time 1910.09 seconds
Started Mar 24 02:01:52 PM PDT 24
Finished Mar 24 02:33:42 PM PDT 24
Peak memory 403052 kb
Host smart-a4354a62-a4c1-42ec-9890-35004e2a5daa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3680873518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_256.3680873518 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_384.4013516092
Short name T532
Test name
Test status
Simulation time 288420342596 ps
CPU time 1798.35 seconds
Started Mar 24 02:01:52 PM PDT 24
Finished Mar 24 02:31:51 PM PDT 24
Peak memory 333888 kb
Host smart-648815c8-7405-4e98-bff4-f62b1b30b4dc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4013516092 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_384.4013516092 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_sha3_512.967837441
Short name T946
Test name
Test status
Simulation time 10952215565 ps
CPU time 1167.85 seconds
Started Mar 24 02:01:53 PM PDT 24
Finished Mar 24 02:21:21 PM PDT 24
Peak memory 302488 kb
Host smart-842aa0f8-ee99-43bf-86ce-0282a62f66d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=967837441 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_sha3_512.967837441 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_128.3822432887
Short name T458
Test name
Test status
Simulation time 122745733064 ps
CPU time 5337.72 seconds
Started Mar 24 02:01:52 PM PDT 24
Finished Mar 24 03:30:50 PM PDT 24
Peak memory 664008 kb
Host smart-8d160b18-693f-4d17-b3f0-81539c0ae95e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3822432887 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_128.3822432887 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/23.kmac_test_vectors_shake_256.433224078
Short name T770
Test name
Test status
Simulation time 302845831458 ps
CPU time 4988.9 seconds
Started Mar 24 02:01:51 PM PDT 24
Finished Mar 24 03:25:01 PM PDT 24
Peak memory 573404 kb
Host smart-382d996d-005b-47df-8ca0-1fb671b4fb96
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=433224078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_test_vectors_shake_256.433224078 +enable_masking=1 +sw_key_masked=0
Directory /workspace/23.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/24.kmac_alert_test.330080128
Short name T850
Test name
Test status
Simulation time 20342104 ps
CPU time 0.96 seconds
Started Mar 24 02:02:21 PM PDT 24
Finished Mar 24 02:02:22 PM PDT 24
Peak memory 218480 kb
Host smart-e080dca7-88a0-45de-bf2f-37c963b6e7a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330080128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_alert_test.330080128 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/24.kmac_alert_test/latest

Test location /workspace/coverage/default/24.kmac_app.4020702267
Short name T255
Test name
Test status
Simulation time 2229375547 ps
CPU time 15.84 seconds
Started Mar 24 02:02:13 PM PDT 24
Finished Mar 24 02:02:29 PM PDT 24
Peak memory 224504 kb
Host smart-0ecc68d9-62aa-4886-8a88-d1390588dbad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020702267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.4020702267 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_app/latest

Test location /workspace/coverage/default/24.kmac_burst_write.357335410
Short name T440
Test name
Test status
Simulation time 13485014511 ps
CPU time 544.55 seconds
Started Mar 24 02:02:03 PM PDT 24
Finished Mar 24 02:11:08 PM PDT 24
Peak memory 235320 kb
Host smart-cb662217-9fd1-4f1b-8f6d-2b12ead09b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357335410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_burst_write.357335410 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_burst_write/latest

Test location /workspace/coverage/default/24.kmac_entropy_refresh.1868565398
Short name T97
Test name
Test status
Simulation time 4978023199 ps
CPU time 82.8 seconds
Started Mar 24 02:02:13 PM PDT 24
Finished Mar 24 02:03:36 PM PDT 24
Peak memory 231908 kb
Host smart-79af598b-1006-43d3-81ac-4e4823a3bcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868565398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_entropy_refresh.1868565398 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/24.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/24.kmac_error.2537204262
Short name T706
Test name
Test status
Simulation time 6663987851 ps
CPU time 280.39 seconds
Started Mar 24 02:02:13 PM PDT 24
Finished Mar 24 02:06:54 PM PDT 24
Peak memory 255284 kb
Host smart-3c425dd9-73c7-424f-b2e4-f576e5c97a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537204262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_error.2537204262 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_error/latest

Test location /workspace/coverage/default/24.kmac_key_error.893889573
Short name T501
Test name
Test status
Simulation time 3823522049 ps
CPU time 4.28 seconds
Started Mar 24 02:02:21 PM PDT 24
Finished Mar 24 02:02:25 PM PDT 24
Peak memory 218648 kb
Host smart-d344707d-b3d0-42c5-8841-fcd0338fec0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893889573 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_key_error.893889573 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_key_error/latest

Test location /workspace/coverage/default/24.kmac_lc_escalation.2849030574
Short name T607
Test name
Test status
Simulation time 48171295 ps
CPU time 1.65 seconds
Started Mar 24 02:02:19 PM PDT 24
Finished Mar 24 02:02:20 PM PDT 24
Peak memory 226676 kb
Host smart-693d9d4a-7c60-43b5-8873-c7daf12bd7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849030574 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.2849030574 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/24.kmac_lc_escalation/latest

Test location /workspace/coverage/default/24.kmac_long_msg_and_output.163247107
Short name T727
Test name
Test status
Simulation time 206621158325 ps
CPU time 1879.04 seconds
Started Mar 24 02:02:03 PM PDT 24
Finished Mar 24 02:33:22 PM PDT 24
Peak memory 378852 kb
Host smart-b0082002-8ef2-4e6d-84b6-5e9eafff63d0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163247107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_long_msg_an
d_output.163247107 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/24.kmac_sideload.2211685868
Short name T929
Test name
Test status
Simulation time 28951834068 ps
CPU time 174.88 seconds
Started Mar 24 02:02:03 PM PDT 24
Finished Mar 24 02:04:58 PM PDT 24
Peak memory 236756 kb
Host smart-292cafb0-ad4e-47a4-8396-f457f0cee131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211685868 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload.2211685868 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_sideload/latest

Test location /workspace/coverage/default/24.kmac_smoke.3312230184
Short name T265
Test name
Test status
Simulation time 16008958519 ps
CPU time 81.92 seconds
Started Mar 24 02:01:57 PM PDT 24
Finished Mar 24 02:03:19 PM PDT 24
Peak memory 219152 kb
Host smart-bb8c97d6-b979-4811-b0bb-6ca852a6adee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312230184 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_smoke.3312230184 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_smoke/latest

Test location /workspace/coverage/default/24.kmac_stress_all.3509828191
Short name T441
Test name
Test status
Simulation time 987649410 ps
CPU time 6.07 seconds
Started Mar 24 02:02:19 PM PDT 24
Finished Mar 24 02:02:25 PM PDT 24
Peak memory 218648 kb
Host smart-be3ebcb0-5d1c-47a0-885e-419a28db6f30
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3509828191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_stress_all.3509828191 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_stress_all/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac.2413423903
Short name T726
Test name
Test status
Simulation time 123011201 ps
CPU time 6.29 seconds
Started Mar 24 02:02:07 PM PDT 24
Finished Mar 24 02:02:14 PM PDT 24
Peak memory 226684 kb
Host smart-cd24509e-e2b2-4b86-9aeb-6b901d0783d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413423903 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 24.kmac_test_vectors_kmac.2413423903 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_kmac_xof.711587837
Short name T875
Test name
Test status
Simulation time 583490460 ps
CPU time 6.34 seconds
Started Mar 24 02:02:13 PM PDT 24
Finished Mar 24 02:02:19 PM PDT 24
Peak memory 218568 kb
Host smart-c6cf337e-9337-467a-ad55-96ea72c3cda3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711587837 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 24.kmac_test_vectors_kmac_xof.711587837 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_224.2037287607
Short name T465
Test name
Test status
Simulation time 22506484506 ps
CPU time 2150.49 seconds
Started Mar 24 02:02:03 PM PDT 24
Finished Mar 24 02:37:54 PM PDT 24
Peak memory 401624 kb
Host smart-98f4fa07-cc79-4b4a-a6f7-0f3ec1fc0a93
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2037287607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_224.2037287607 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_384.1198024465
Short name T109
Test name
Test status
Simulation time 63041083642 ps
CPU time 1694.21 seconds
Started Mar 24 02:02:06 PM PDT 24
Finished Mar 24 02:30:21 PM PDT 24
Peak memory 341660 kb
Host smart-93d20e0f-9909-480c-ae23-eff6ab4aa189
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1198024465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_384.1198024465 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_sha3_512.1364785139
Short name T970
Test name
Test status
Simulation time 48110032083 ps
CPU time 1307.44 seconds
Started Mar 24 02:02:08 PM PDT 24
Finished Mar 24 02:23:56 PM PDT 24
Peak memory 296204 kb
Host smart-d16c3466-963d-4c62-84b3-b1f63a442947
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1364785139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_sha3_512.1364785139 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_128.3899001606
Short name T802
Test name
Test status
Simulation time 319518067774 ps
CPU time 5164.03 seconds
Started Mar 24 02:02:08 PM PDT 24
Finished Mar 24 03:28:13 PM PDT 24
Peak memory 651936 kb
Host smart-cf0a2852-777d-4ef7-8ac7-ca316159104f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3899001606 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_128.3899001606 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/24.kmac_test_vectors_shake_256.1304814235
Short name T340
Test name
Test status
Simulation time 153523631322 ps
CPU time 4841.27 seconds
Started Mar 24 02:02:08 PM PDT 24
Finished Mar 24 03:22:50 PM PDT 24
Peak memory 575760 kb
Host smart-cb65f73c-3fab-4284-aab3-fab54bea3a1c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1304814235 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_test_vectors_shake_256.1304814235 +enable_masking=1 +sw_key_masked=0
Directory /workspace/24.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/25.kmac_alert_test.1732416356
Short name T44
Test name
Test status
Simulation time 19392579 ps
CPU time 0.87 seconds
Started Mar 24 02:02:39 PM PDT 24
Finished Mar 24 02:02:40 PM PDT 24
Peak memory 220476 kb
Host smart-f632bfa4-0c38-48ca-bfa8-1365caa365a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732416356 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_alert_test.1732416356 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_alert_test/latest

Test location /workspace/coverage/default/25.kmac_app.1257402267
Short name T393
Test name
Test status
Simulation time 12584239664 ps
CPU time 332.94 seconds
Started Mar 24 02:02:29 PM PDT 24
Finished Mar 24 02:08:02 PM PDT 24
Peak memory 250704 kb
Host smart-e9b275c0-341e-4e95-b1df-3ab81c6cdd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257402267 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_app.1257402267 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_app/latest

Test location /workspace/coverage/default/25.kmac_burst_write.3785994000
Short name T358
Test name
Test status
Simulation time 9103374714 ps
CPU time 831.26 seconds
Started Mar 24 02:02:24 PM PDT 24
Finished Mar 24 02:16:15 PM PDT 24
Peak memory 243136 kb
Host smart-f5e91f3e-a0b8-4e9e-a8e9-7a15bf708789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785994000 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_burst_write.3785994000 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_burst_write/latest

Test location /workspace/coverage/default/25.kmac_entropy_refresh.3917927089
Short name T34
Test name
Test status
Simulation time 22137881960 ps
CPU time 194.38 seconds
Started Mar 24 02:02:33 PM PDT 24
Finished Mar 24 02:05:48 PM PDT 24
Peak memory 240636 kb
Host smart-8730c716-baff-4934-a296-6763ae2b8437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917927089 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_entropy_refresh.3917927089 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/25.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/25.kmac_error.2828800933
Short name T655
Test name
Test status
Simulation time 2838089704 ps
CPU time 85.92 seconds
Started Mar 24 02:02:34 PM PDT 24
Finished Mar 24 02:04:00 PM PDT 24
Peak memory 243140 kb
Host smart-825c3337-6d40-49c0-9143-574ed66a0d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828800933 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_error.2828800933 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_error/latest

Test location /workspace/coverage/default/25.kmac_key_error.3897615965
Short name T427
Test name
Test status
Simulation time 168235554 ps
CPU time 1.57 seconds
Started Mar 24 02:02:36 PM PDT 24
Finished Mar 24 02:02:38 PM PDT 24
Peak memory 218552 kb
Host smart-123ee835-4429-484a-a606-56bfef080de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897615965 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_key_error.3897615965 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_key_error/latest

Test location /workspace/coverage/default/25.kmac_lc_escalation.3540806587
Short name T61
Test name
Test status
Simulation time 3549561325 ps
CPU time 21.04 seconds
Started Mar 24 02:02:33 PM PDT 24
Finished Mar 24 02:02:54 PM PDT 24
Peak memory 231984 kb
Host smart-6251eb73-9383-4769-a6fe-c52207b5283d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540806587 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.3540806587 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/25.kmac_lc_escalation/latest

Test location /workspace/coverage/default/25.kmac_long_msg_and_output.2684337940
Short name T181
Test name
Test status
Simulation time 208688201856 ps
CPU time 1180.61 seconds
Started Mar 24 02:02:20 PM PDT 24
Finished Mar 24 02:22:01 PM PDT 24
Peak memory 320836 kb
Host smart-f2b01a06-0cdb-4cd8-93ac-543e8bdeb413
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2684337940 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_long_msg_a
nd_output.2684337940 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/25.kmac_sideload.2958809214
Short name T613
Test name
Test status
Simulation time 4847578804 ps
CPU time 135.5 seconds
Started Mar 24 02:02:24 PM PDT 24
Finished Mar 24 02:04:40 PM PDT 24
Peak memory 232660 kb
Host smart-e871f6ee-5471-4d3d-aa46-bb16465460f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958809214 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload.2958809214 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_sideload/latest

Test location /workspace/coverage/default/25.kmac_smoke.1942779788
Short name T448
Test name
Test status
Simulation time 1469847086 ps
CPU time 26.21 seconds
Started Mar 24 02:02:20 PM PDT 24
Finished Mar 24 02:02:46 PM PDT 24
Peak memory 226720 kb
Host smart-0b37bac4-dfac-453b-9f8a-224ac1b1a1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942779788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_smoke.1942779788 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_smoke/latest

Test location /workspace/coverage/default/25.kmac_stress_all.3273406591
Short name T1040
Test name
Test status
Simulation time 10179558956 ps
CPU time 239.87 seconds
Started Mar 24 02:02:35 PM PDT 24
Finished Mar 24 02:06:35 PM PDT 24
Peak memory 267728 kb
Host smart-ad0afa03-0a60-47b0-9e0f-58c3368e3a1b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3273406591 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_stress_all.3273406591 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_stress_all/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac.1943978285
Short name T1010
Test name
Test status
Simulation time 183686100 ps
CPU time 5.76 seconds
Started Mar 24 02:02:29 PM PDT 24
Finished Mar 24 02:02:35 PM PDT 24
Peak memory 218672 kb
Host smart-1e158ffd-b599-4919-83e1-5525524b3aaf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943978285 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 25.kmac_test_vectors_kmac.1943978285 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_kmac_xof.2187101134
Short name T635
Test name
Test status
Simulation time 1023623465 ps
CPU time 7.47 seconds
Started Mar 24 02:02:29 PM PDT 24
Finished Mar 24 02:02:37 PM PDT 24
Peak memory 226652 kb
Host smart-15d0d9ac-d7ea-4f0c-a854-c01e7c280f6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187101134 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 25.kmac_test_vectors_kmac_xof.2187101134 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_224.3781383443
Short name T789
Test name
Test status
Simulation time 21477018110 ps
CPU time 1953.03 seconds
Started Mar 24 02:02:24 PM PDT 24
Finished Mar 24 02:34:58 PM PDT 24
Peak memory 400324 kb
Host smart-9123fe19-b569-4ca7-8216-392112c06361
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3781383443 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_224.3781383443 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_256.2359424884
Short name T616
Test name
Test status
Simulation time 78116402514 ps
CPU time 1733.26 seconds
Started Mar 24 02:02:24 PM PDT 24
Finished Mar 24 02:31:18 PM PDT 24
Peak memory 378120 kb
Host smart-48ad64e9-1e8e-4b00-a785-85639ebc6d64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2359424884 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_256.2359424884 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_384.4094985857
Short name T423
Test name
Test status
Simulation time 198740598263 ps
CPU time 1646.55 seconds
Started Mar 24 02:02:25 PM PDT 24
Finished Mar 24 02:29:51 PM PDT 24
Peak memory 334532 kb
Host smart-623d36d7-7293-4b71-a055-890c96b6e057
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4094985857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_384.4094985857 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_sha3_512.1262214436
Short name T220
Test name
Test status
Simulation time 41702661408 ps
CPU time 1095.44 seconds
Started Mar 24 02:02:23 PM PDT 24
Finished Mar 24 02:20:39 PM PDT 24
Peak memory 301016 kb
Host smart-45501992-9b55-4c09-9db2-b0a375be3055
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1262214436 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_sha3_512.1262214436 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_128.2027513322
Short name T289
Test name
Test status
Simulation time 354702137126 ps
CPU time 5781.21 seconds
Started Mar 24 02:02:24 PM PDT 24
Finished Mar 24 03:38:46 PM PDT 24
Peak memory 657124 kb
Host smart-f138979a-5619-4119-bb99-31fc91227658
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2027513322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_128.2027513322 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/25.kmac_test_vectors_shake_256.486207304
Short name T772
Test name
Test status
Simulation time 113338478932 ps
CPU time 4646.01 seconds
Started Mar 24 02:02:28 PM PDT 24
Finished Mar 24 03:19:55 PM PDT 24
Peak memory 570916 kb
Host smart-1864a6c4-b8c3-48de-96cc-929bb281d41f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=486207304 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_test_vectors_shake_256.486207304 +enable_masking=1 +sw_key_masked=0
Directory /workspace/25.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/26.kmac_alert_test.516971627
Short name T845
Test name
Test status
Simulation time 28729555 ps
CPU time 0.79 seconds
Started Mar 24 02:02:57 PM PDT 24
Finished Mar 24 02:02:58 PM PDT 24
Peak memory 218448 kb
Host smart-73735b21-e9d8-471a-a206-9a93a08cc526
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516971627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_alert_test.516971627 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/26.kmac_alert_test/latest

Test location /workspace/coverage/default/26.kmac_app.3859765864
Short name T454
Test name
Test status
Simulation time 69209859574 ps
CPU time 241.45 seconds
Started Mar 24 02:02:48 PM PDT 24
Finished Mar 24 02:06:49 PM PDT 24
Peak memory 244504 kb
Host smart-cb747d8c-c989-4971-b7cc-2fc1ab4eb23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859765864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_app.3859765864 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_app/latest

Test location /workspace/coverage/default/26.kmac_burst_write.1543702217
Short name T327
Test name
Test status
Simulation time 43418792691 ps
CPU time 770.81 seconds
Started Mar 24 02:02:39 PM PDT 24
Finished Mar 24 02:15:30 PM PDT 24
Peak memory 237008 kb
Host smart-396d75c8-38f8-4f54-bd98-c1d02e463e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543702217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_burst_write.1543702217 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_burst_write/latest

Test location /workspace/coverage/default/26.kmac_entropy_refresh.3434016419
Short name T930
Test name
Test status
Simulation time 561425752 ps
CPU time 24.68 seconds
Started Mar 24 02:02:52 PM PDT 24
Finished Mar 24 02:03:19 PM PDT 24
Peak memory 226744 kb
Host smart-b03113a2-b0fc-4963-aaf6-60e9f05eb0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434016419 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_entropy_refresh.3434016419 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/26.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/26.kmac_error.1290936687
Short name T372
Test name
Test status
Simulation time 5849896528 ps
CPU time 294.03 seconds
Started Mar 24 02:02:52 PM PDT 24
Finished Mar 24 02:07:46 PM PDT 24
Peak memory 259524 kb
Host smart-f85db20b-5840-407e-a713-031307f3a158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290936687 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_error.1290936687 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_error/latest

Test location /workspace/coverage/default/26.kmac_key_error.2727179823
Short name T382
Test name
Test status
Simulation time 15622468155 ps
CPU time 6.62 seconds
Started Mar 24 02:02:52 PM PDT 24
Finished Mar 24 02:03:01 PM PDT 24
Peak memory 218596 kb
Host smart-34991665-a0fe-4cce-b377-5c9133d88b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727179823 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_key_error.2727179823 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_key_error/latest

Test location /workspace/coverage/default/26.kmac_lc_escalation.3173812037
Short name T843
Test name
Test status
Simulation time 51371150 ps
CPU time 1.47 seconds
Started Mar 24 02:02:57 PM PDT 24
Finished Mar 24 02:02:59 PM PDT 24
Peak memory 219488 kb
Host smart-35fde305-ee4e-49d2-aba0-732a010da843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3173812037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.3173812037 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/26.kmac_lc_escalation/latest

Test location /workspace/coverage/default/26.kmac_long_msg_and_output.2035728435
Short name T124
Test name
Test status
Simulation time 23052283195 ps
CPU time 2538.16 seconds
Started Mar 24 02:02:36 PM PDT 24
Finished Mar 24 02:44:55 PM PDT 24
Peak memory 428176 kb
Host smart-8516f954-449f-4c4d-a402-7af7fe210ac9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035728435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_long_msg_a
nd_output.2035728435 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/26.kmac_sideload.2496348431
Short name T691
Test name
Test status
Simulation time 23514576555 ps
CPU time 558.04 seconds
Started Mar 24 02:02:38 PM PDT 24
Finished Mar 24 02:11:56 PM PDT 24
Peak memory 255872 kb
Host smart-89019e9b-3153-49a6-93ea-554732beafe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496348431 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload.2496348431 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_sideload/latest

Test location /workspace/coverage/default/26.kmac_smoke.2627724358
Short name T1063
Test name
Test status
Simulation time 736783293 ps
CPU time 18.54 seconds
Started Mar 24 02:02:39 PM PDT 24
Finished Mar 24 02:02:58 PM PDT 24
Peak memory 226952 kb
Host smart-4a7270c5-f9bc-4ead-89af-1d14709a423d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2627724358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_smoke.2627724358 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_smoke/latest

Test location /workspace/coverage/default/26.kmac_stress_all.692066873
Short name T827
Test name
Test status
Simulation time 338664041627 ps
CPU time 2884.37 seconds
Started Mar 24 02:02:52 PM PDT 24
Finished Mar 24 02:51:00 PM PDT 24
Peak memory 488424 kb
Host smart-d8862d6d-037d-487c-9f6f-b3aa7a703e23
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=692066873 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_stress_all.692066873 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_stress_all/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac.3497330502
Short name T773
Test name
Test status
Simulation time 522741133 ps
CPU time 6.23 seconds
Started Mar 24 02:02:47 PM PDT 24
Finished Mar 24 02:02:54 PM PDT 24
Peak memory 218696 kb
Host smart-65df0151-fb5e-4614-943f-82f9c9efd2c5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497330502 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 26.kmac_test_vectors_kmac.3497330502 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_kmac_xof.1681267353
Short name T292
Test name
Test status
Simulation time 471340873 ps
CPU time 5.95 seconds
Started Mar 24 02:02:48 PM PDT 24
Finished Mar 24 02:02:54 PM PDT 24
Peak memory 219612 kb
Host smart-8e06cb86-7bd0-4b09-9bb4-1fcb9f2875d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1681267353 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 26.kmac_test_vectors_kmac_xof.1681267353 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_224.1419513061
Short name T371
Test name
Test status
Simulation time 138747077671 ps
CPU time 2255.36 seconds
Started Mar 24 02:02:44 PM PDT 24
Finished Mar 24 02:40:20 PM PDT 24
Peak memory 402684 kb
Host smart-bb3c009c-8411-4d48-9d70-cc1a23c29076
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1419513061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_224.1419513061 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_384.4241569706
Short name T972
Test name
Test status
Simulation time 80109354306 ps
CPU time 1568.23 seconds
Started Mar 24 02:02:50 PM PDT 24
Finished Mar 24 02:29:00 PM PDT 24
Peak memory 347252 kb
Host smart-c523ba83-6507-4a36-84fd-ad0ca8e7e645
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4241569706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_384.4241569706 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_sha3_512.1133224747
Short name T618
Test name
Test status
Simulation time 99588778216 ps
CPU time 1389.4 seconds
Started Mar 24 02:02:50 PM PDT 24
Finished Mar 24 02:26:01 PM PDT 24
Peak memory 299676 kb
Host smart-0ad4b69a-0897-46c1-9df7-24af041d51e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1133224747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_sha3_512.1133224747 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_128.2769049308
Short name T1
Test name
Test status
Simulation time 613751746921 ps
CPU time 5563.64 seconds
Started Mar 24 02:02:48 PM PDT 24
Finished Mar 24 03:35:33 PM PDT 24
Peak memory 665964 kb
Host smart-425d5656-b4fe-4aa2-97ba-710f8f50e373
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2769049308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_128.2769049308 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/26.kmac_test_vectors_shake_256.113263486
Short name T936
Test name
Test status
Simulation time 222252791464 ps
CPU time 4112.16 seconds
Started Mar 24 02:02:48 PM PDT 24
Finished Mar 24 03:11:21 PM PDT 24
Peak memory 558916 kb
Host smart-c4574893-ec1e-43ba-9a16-a9d111510826
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=113263486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_test_vectors_shake_256.113263486 +enable_masking=1 +sw_key_masked=0
Directory /workspace/26.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/27.kmac_alert_test.2150781339
Short name T307
Test name
Test status
Simulation time 29047985 ps
CPU time 0.88 seconds
Started Mar 24 02:03:15 PM PDT 24
Finished Mar 24 02:03:16 PM PDT 24
Peak memory 218720 kb
Host smart-670d2318-ff57-4482-9462-e949639658d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150781339 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_alert_test.2150781339 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_alert_test/latest

Test location /workspace/coverage/default/27.kmac_app.1319082057
Short name T271
Test name
Test status
Simulation time 1561625475 ps
CPU time 66.22 seconds
Started Mar 24 02:03:08 PM PDT 24
Finished Mar 24 02:04:14 PM PDT 24
Peak memory 230368 kb
Host smart-a00bc6dd-83c3-4109-936e-13c75d187c0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319082057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_app.1319082057 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_app/latest

Test location /workspace/coverage/default/27.kmac_burst_write.3658592331
Short name T261
Test name
Test status
Simulation time 1182738169 ps
CPU time 106.09 seconds
Started Mar 24 02:02:58 PM PDT 24
Finished Mar 24 02:04:45 PM PDT 24
Peak memory 226716 kb
Host smart-7877973a-45a5-4de8-97e9-d726eaf3be65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658592331 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_burst_write.3658592331 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_burst_write/latest

Test location /workspace/coverage/default/27.kmac_entropy_refresh.689394801
Short name T326
Test name
Test status
Simulation time 49818223363 ps
CPU time 242.73 seconds
Started Mar 24 02:03:07 PM PDT 24
Finished Mar 24 02:07:10 PM PDT 24
Peak memory 245088 kb
Host smart-1d7eb520-7e1b-4841-9b4b-629b192b8d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689394801 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_entropy_refresh.689394801 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/27.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/27.kmac_error.3625013775
Short name T1006
Test name
Test status
Simulation time 8340266602 ps
CPU time 167.43 seconds
Started Mar 24 02:03:07 PM PDT 24
Finished Mar 24 02:05:55 PM PDT 24
Peak memory 254456 kb
Host smart-d95b4660-7ad9-4e4d-be37-95e9bb925ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625013775 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_error.3625013775 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_error/latest

Test location /workspace/coverage/default/27.kmac_key_error.37873848
Short name T582
Test name
Test status
Simulation time 4074077234 ps
CPU time 5.22 seconds
Started Mar 24 02:03:13 PM PDT 24
Finished Mar 24 02:03:18 PM PDT 24
Peak memory 223504 kb
Host smart-e4ec6a38-85ef-4f3b-bb7e-f3b8f40f7e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37873848 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_key_error.37873848 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_key_error/latest

Test location /workspace/coverage/default/27.kmac_lc_escalation.868239428
Short name T759
Test name
Test status
Simulation time 998107966 ps
CPU time 32.47 seconds
Started Mar 24 02:03:13 PM PDT 24
Finished Mar 24 02:03:46 PM PDT 24
Peak memory 235824 kb
Host smart-b159fc1c-833c-43bd-a1e6-ef6aeadc499f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868239428 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.868239428 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/27.kmac_lc_escalation/latest

Test location /workspace/coverage/default/27.kmac_long_msg_and_output.12675203
Short name T766
Test name
Test status
Simulation time 10854067810 ps
CPU time 1010.9 seconds
Started Mar 24 02:02:58 PM PDT 24
Finished Mar 24 02:19:49 PM PDT 24
Peak memory 321888 kb
Host smart-e66ca1cd-73e7-48d9-9ffb-2746f0a0f3fc
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12675203 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_long_msg_and
_output.12675203 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/27.kmac_sideload.658098875
Short name T494
Test name
Test status
Simulation time 15784242285 ps
CPU time 317.27 seconds
Started Mar 24 02:02:58 PM PDT 24
Finished Mar 24 02:08:16 PM PDT 24
Peak memory 247600 kb
Host smart-8a1cd896-0f3a-4f68-80cb-51ef37557b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658098875 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload.658098875 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_sideload/latest

Test location /workspace/coverage/default/27.kmac_smoke.4039662368
Short name T948
Test name
Test status
Simulation time 2004196706 ps
CPU time 31.02 seconds
Started Mar 24 02:02:52 PM PDT 24
Finished Mar 24 02:03:26 PM PDT 24
Peak memory 226688 kb
Host smart-2a515cb9-6367-4b3e-a280-fdcd11ab6ddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039662368 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_smoke.4039662368 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_smoke/latest

Test location /workspace/coverage/default/27.kmac_stress_all.2920236663
Short name T335
Test name
Test status
Simulation time 107894954557 ps
CPU time 2463.58 seconds
Started Mar 24 02:03:12 PM PDT 24
Finished Mar 24 02:44:16 PM PDT 24
Peak memory 471700 kb
Host smart-afe37447-39d5-4018-bc07-136969b6c65b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2920236663 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all.2920236663 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all/latest

Test location /workspace/coverage/default/27.kmac_stress_all_with_rand_reset.855196395
Short name T565
Test name
Test status
Simulation time 97496066213 ps
CPU time 1239.55 seconds
Started Mar 24 02:03:13 PM PDT 24
Finished Mar 24 02:23:53 PM PDT 24
Peak memory 305296 kb
Host smart-9fec8cdb-1b62-4947-a08b-1fc3b2a9abee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=855196395 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_stress_all_with_rand_reset.855196395 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac.666063200
Short name T1001
Test name
Test status
Simulation time 363553599 ps
CPU time 6.71 seconds
Started Mar 24 02:03:10 PM PDT 24
Finished Mar 24 02:03:17 PM PDT 24
Peak memory 226700 kb
Host smart-1dd8d6d3-6d8f-4380-b11c-cfade80384b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666063200 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 27.kmac_test_vectors_kmac.666063200 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_kmac_xof.3636284689
Short name T194
Test name
Test status
Simulation time 841464127 ps
CPU time 6.76 seconds
Started Mar 24 02:03:07 PM PDT 24
Finished Mar 24 02:03:14 PM PDT 24
Peak memory 226700 kb
Host smart-249d92cf-efcb-4edc-9cee-e1d52f4719e9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636284689 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 27.kmac_test_vectors_kmac_xof.3636284689 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_224.1008290375
Short name T377
Test name
Test status
Simulation time 718244910418 ps
CPU time 2447.42 seconds
Started Mar 24 02:02:57 PM PDT 24
Finished Mar 24 02:43:45 PM PDT 24
Peak memory 393440 kb
Host smart-64dd73e2-1cdc-4182-9946-43b6b98d6155
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1008290375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_224.1008290375 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_256.630994819
Short name T680
Test name
Test status
Simulation time 39237887695 ps
CPU time 1877.28 seconds
Started Mar 24 02:02:58 PM PDT 24
Finished Mar 24 02:34:15 PM PDT 24
Peak memory 387656 kb
Host smart-3a7938bd-cafb-460f-a05a-8490abb3ab61
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=630994819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_256.630994819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_384.899200987
Short name T796
Test name
Test status
Simulation time 70179233229 ps
CPU time 1720.02 seconds
Started Mar 24 02:02:57 PM PDT 24
Finished Mar 24 02:31:38 PM PDT 24
Peak memory 335712 kb
Host smart-fe4827b6-8d3c-4c44-9845-67cbb9403e14
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=899200987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_384.899200987 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_sha3_512.1255365390
Short name T524
Test name
Test status
Simulation time 97251973778 ps
CPU time 1355.91 seconds
Started Mar 24 02:02:57 PM PDT 24
Finished Mar 24 02:25:33 PM PDT 24
Peak memory 305856 kb
Host smart-3eba9e18-2e0f-4542-810c-ab87b20488cc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1255365390 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_sha3_512.1255365390 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_128.57101042
Short name T488
Test name
Test status
Simulation time 1197127189824 ps
CPU time 6432.31 seconds
Started Mar 24 02:03:03 PM PDT 24
Finished Mar 24 03:50:16 PM PDT 24
Peak memory 657572 kb
Host smart-8ae0577b-055f-4fa1-a082-e3c128846db6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=57101042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_128.57101042 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/27.kmac_test_vectors_shake_256.3043014219
Short name T421
Test name
Test status
Simulation time 2410985490724 ps
CPU time 6190.63 seconds
Started Mar 24 02:03:02 PM PDT 24
Finished Mar 24 03:46:14 PM PDT 24
Peak memory 565396 kb
Host smart-baca1d63-6c63-4c5d-b988-b7c752295358
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3043014219 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_test_vectors_shake_256.3043014219 +enable_masking=1 +sw_key_masked=0
Directory /workspace/27.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/28.kmac_alert_test.3187674015
Short name T924
Test name
Test status
Simulation time 16512799 ps
CPU time 0.84 seconds
Started Mar 24 02:03:40 PM PDT 24
Finished Mar 24 02:03:41 PM PDT 24
Peak memory 218724 kb
Host smart-719b59e3-e17b-4ac3-86ea-38db761645cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187674015 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_alert_test.3187674015 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_alert_test/latest

Test location /workspace/coverage/default/28.kmac_app.1463335374
Short name T402
Test name
Test status
Simulation time 2978029379 ps
CPU time 139.31 seconds
Started Mar 24 02:03:35 PM PDT 24
Finished Mar 24 02:05:54 PM PDT 24
Peak memory 236488 kb
Host smart-a958fc61-f506-4a5d-9d8b-cc33ec0394ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463335374 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_app.1463335374 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_app/latest

Test location /workspace/coverage/default/28.kmac_burst_write.2533625201
Short name T897
Test name
Test status
Simulation time 66085446662 ps
CPU time 1084.39 seconds
Started Mar 24 02:03:24 PM PDT 24
Finished Mar 24 02:21:33 PM PDT 24
Peak memory 237464 kb
Host smart-205eaf1a-58b1-461e-8b71-bcf3d7fb6a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533625201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_burst_write.2533625201 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_burst_write/latest

Test location /workspace/coverage/default/28.kmac_entropy_refresh.903968137
Short name T63
Test name
Test status
Simulation time 30662772138 ps
CPU time 383.43 seconds
Started Mar 24 02:03:34 PM PDT 24
Finished Mar 24 02:09:57 PM PDT 24
Peak memory 251204 kb
Host smart-664112a6-c4cb-4968-8e3e-8439488762a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903968137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_entropy_refresh.903968137 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/28.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/28.kmac_error.1388125453
Short name T685
Test name
Test status
Simulation time 13016253266 ps
CPU time 436.89 seconds
Started Mar 24 02:03:33 PM PDT 24
Finished Mar 24 02:10:50 PM PDT 24
Peak memory 267772 kb
Host smart-b1c5d491-e9fe-40fa-b320-ab088dc4293e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388125453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_error.1388125453 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_error/latest

Test location /workspace/coverage/default/28.kmac_key_error.3634785815
Short name T473
Test name
Test status
Simulation time 144659102 ps
CPU time 1.57 seconds
Started Mar 24 02:03:35 PM PDT 24
Finished Mar 24 02:03:37 PM PDT 24
Peak memory 218592 kb
Host smart-9723fa6a-f72f-49af-a1d3-b3819ae24f20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634785815 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_key_error.3634785815 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_key_error/latest

Test location /workspace/coverage/default/28.kmac_lc_escalation.3639304945
Short name T29
Test name
Test status
Simulation time 49142103 ps
CPU time 1.34 seconds
Started Mar 24 02:03:36 PM PDT 24
Finished Mar 24 02:03:37 PM PDT 24
Peak memory 218832 kb
Host smart-6f1aa694-303f-43e6-bb2e-ef9a096fe257
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3639304945 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.3639304945 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/28.kmac_lc_escalation/latest

Test location /workspace/coverage/default/28.kmac_long_msg_and_output.2905178947
Short name T528
Test name
Test status
Simulation time 104555563564 ps
CPU time 679.79 seconds
Started Mar 24 02:03:21 PM PDT 24
Finished Mar 24 02:14:41 PM PDT 24
Peak memory 275476 kb
Host smart-e36c7627-cf49-4382-b3f8-959381573d2e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905178947 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_long_msg_a
nd_output.2905178947 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/28.kmac_sideload.4255064557
Short name T333
Test name
Test status
Simulation time 21219084371 ps
CPU time 331.2 seconds
Started Mar 24 02:03:18 PM PDT 24
Finished Mar 24 02:08:50 PM PDT 24
Peak memory 247548 kb
Host smart-ecb34143-340a-4aab-8524-1bd725085c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255064557 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload.4255064557 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_sideload/latest

Test location /workspace/coverage/default/28.kmac_smoke.146020804
Short name T360
Test name
Test status
Simulation time 9918598137 ps
CPU time 48.72 seconds
Started Mar 24 02:03:19 PM PDT 24
Finished Mar 24 02:04:09 PM PDT 24
Peak memory 226728 kb
Host smart-1b5f20dd-742f-48db-8e15-0065b6388b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146020804 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_smoke.146020804 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_smoke/latest

Test location /workspace/coverage/default/28.kmac_stress_all.894023470
Short name T963
Test name
Test status
Simulation time 60293143785 ps
CPU time 3116.93 seconds
Started Mar 24 02:03:40 PM PDT 24
Finished Mar 24 02:55:37 PM PDT 24
Peak memory 494096 kb
Host smart-331d4520-9ef3-4854-bded-c41254cc76f7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=894023470 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_stress_all.894023470 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_stress_all/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac.2642515143
Short name T954
Test name
Test status
Simulation time 219100407 ps
CPU time 6.54 seconds
Started Mar 24 02:03:29 PM PDT 24
Finished Mar 24 02:03:37 PM PDT 24
Peak memory 226756 kb
Host smart-fc3be5b4-eaf2-40b2-84d9-0b6daa4a92c0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642515143 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 28.kmac_test_vectors_kmac.2642515143 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_kmac_xof.4078548728
Short name T424
Test name
Test status
Simulation time 422220022 ps
CPU time 7.41 seconds
Started Mar 24 02:03:30 PM PDT 24
Finished Mar 24 02:03:38 PM PDT 24
Peak memory 226476 kb
Host smart-d78b6c7c-f14f-48fa-afc4-9dd1aad38b6c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078548728 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 28.kmac_test_vectors_kmac_xof.4078548728 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_224.3491674115
Short name T1061
Test name
Test status
Simulation time 97959596944 ps
CPU time 2129.55 seconds
Started Mar 24 02:03:25 PM PDT 24
Finished Mar 24 02:38:59 PM PDT 24
Peak memory 396664 kb
Host smart-92a7de90-d38d-4d71-b176-eabc920031b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3491674115 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_224.3491674115 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_256.2358264322
Short name T729
Test name
Test status
Simulation time 27749925438 ps
CPU time 1992.24 seconds
Started Mar 24 02:03:25 PM PDT 24
Finished Mar 24 02:36:41 PM PDT 24
Peak memory 394512 kb
Host smart-21c6db1c-7a3b-4603-aa2c-6b6c2776f78e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2358264322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_256.2358264322 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_384.2465005078
Short name T426
Test name
Test status
Simulation time 147546952112 ps
CPU time 1428.07 seconds
Started Mar 24 02:03:29 PM PDT 24
Finished Mar 24 02:27:18 PM PDT 24
Peak memory 337248 kb
Host smart-33f52afc-bc04-4fb1-998f-244e8bf88db0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2465005078 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_384.2465005078 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_sha3_512.3270091268
Short name T1028
Test name
Test status
Simulation time 47866178355 ps
CPU time 1163.55 seconds
Started Mar 24 02:03:34 PM PDT 24
Finished Mar 24 02:22:58 PM PDT 24
Peak memory 301224 kb
Host smart-93ff08c2-e553-47b0-bc6f-66c591196eaa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3270091268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_sha3_512.3270091268 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_128.914659539
Short name T870
Test name
Test status
Simulation time 351781995607 ps
CPU time 4905.94 seconds
Started Mar 24 02:03:30 PM PDT 24
Finished Mar 24 03:25:17 PM PDT 24
Peak memory 650880 kb
Host smart-addb7d3d-2354-4fae-8d40-0dbcd3aa919d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=914659539 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_128.914659539 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/28.kmac_test_vectors_shake_256.3892762300
Short name T190
Test name
Test status
Simulation time 217906909308 ps
CPU time 4551.8 seconds
Started Mar 24 02:03:28 PM PDT 24
Finished Mar 24 03:19:22 PM PDT 24
Peak memory 561732 kb
Host smart-0e213dd3-726b-4f2a-b4a1-ad79f1816a81
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3892762300 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_test_vectors_shake_256.3892762300 +enable_masking=1 +sw_key_masked=0
Directory /workspace/28.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/29.kmac_alert_test.3577835290
Short name T403
Test name
Test status
Simulation time 143084076 ps
CPU time 0.81 seconds
Started Mar 24 02:04:13 PM PDT 24
Finished Mar 24 02:04:15 PM PDT 24
Peak memory 218504 kb
Host smart-0c39e6b1-f8b8-4965-aebf-98050c33e089
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577835290 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_alert_test.3577835290 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_alert_test/latest

Test location /workspace/coverage/default/29.kmac_app.859895026
Short name T877
Test name
Test status
Simulation time 45965421750 ps
CPU time 380.28 seconds
Started Mar 24 02:03:57 PM PDT 24
Finished Mar 24 02:10:17 PM PDT 24
Peak memory 251624 kb
Host smart-9e82fb55-c479-4f31-9160-2888625aaf47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859895026 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_app.859895026 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_app/latest

Test location /workspace/coverage/default/29.kmac_burst_write.2544675205
Short name T302
Test name
Test status
Simulation time 73910689734 ps
CPU time 1396.25 seconds
Started Mar 24 02:03:53 PM PDT 24
Finished Mar 24 02:27:10 PM PDT 24
Peak memory 240088 kb
Host smart-a44f61f2-a4e7-4430-a798-9fb4f99b445f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544675205 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_burst_write.2544675205 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_burst_write/latest

Test location /workspace/coverage/default/29.kmac_entropy_refresh.1954272206
Short name T1020
Test name
Test status
Simulation time 822546301 ps
CPU time 16.68 seconds
Started Mar 24 02:03:55 PM PDT 24
Finished Mar 24 02:04:12 PM PDT 24
Peak memory 226720 kb
Host smart-e145c846-fcb1-4c9d-886e-17374881f8ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954272206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_entropy_refresh.1954272206 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/29.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/29.kmac_error.1859245607
Short name T775
Test name
Test status
Simulation time 832800004 ps
CPU time 11.5 seconds
Started Mar 24 02:04:01 PM PDT 24
Finished Mar 24 02:04:12 PM PDT 24
Peak memory 226684 kb
Host smart-1044c7cf-e1ec-4fde-8014-d7c8011f1100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859245607 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_error.1859245607 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_error/latest

Test location /workspace/coverage/default/29.kmac_key_error.4256087850
Short name T267
Test name
Test status
Simulation time 400670044 ps
CPU time 1.22 seconds
Started Mar 24 02:04:08 PM PDT 24
Finished Mar 24 02:04:10 PM PDT 24
Peak memory 218240 kb
Host smart-338f53a6-3b4c-4f78-a440-923466b10161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256087850 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_key_error.4256087850 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_key_error/latest

Test location /workspace/coverage/default/29.kmac_lc_escalation.945517336
Short name T652
Test name
Test status
Simulation time 228408749 ps
CPU time 1.54 seconds
Started Mar 24 02:04:09 PM PDT 24
Finished Mar 24 02:04:11 PM PDT 24
Peak memory 219480 kb
Host smart-a6baa899-6dfb-4d74-9d06-5d0a2a4ad94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945517336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.945517336 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/29.kmac_lc_escalation/latest

Test location /workspace/coverage/default/29.kmac_long_msg_and_output.1466944997
Short name T555
Test name
Test status
Simulation time 14894949555 ps
CPU time 365.28 seconds
Started Mar 24 02:03:44 PM PDT 24
Finished Mar 24 02:09:50 PM PDT 24
Peak memory 251368 kb
Host smart-7cfa1911-1504-4a3c-a1a6-74391945741c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466944997 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_long_msg_a
nd_output.1466944997 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/29.kmac_sideload.880515424
Short name T964
Test name
Test status
Simulation time 54543683483 ps
CPU time 451.63 seconds
Started Mar 24 02:03:53 PM PDT 24
Finished Mar 24 02:11:25 PM PDT 24
Peak memory 252508 kb
Host smart-a0b7e1b0-f3d3-4838-881a-96d05b0f7636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880515424 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload.880515424 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_sideload/latest

Test location /workspace/coverage/default/29.kmac_smoke.1225956881
Short name T900
Test name
Test status
Simulation time 4762693371 ps
CPU time 26.36 seconds
Started Mar 24 02:03:44 PM PDT 24
Finished Mar 24 02:04:11 PM PDT 24
Peak memory 222800 kb
Host smart-1e4ae0c7-9cdb-418e-9c76-38695bd03dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225956881 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_smoke.1225956881 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_smoke/latest

Test location /workspace/coverage/default/29.kmac_stress_all.3014479596
Short name T67
Test name
Test status
Simulation time 15829948803 ps
CPU time 608.98 seconds
Started Mar 24 02:04:09 PM PDT 24
Finished Mar 24 02:14:18 PM PDT 24
Peak memory 292512 kb
Host smart-bad39d3d-87df-4778-ad84-25ec26524541
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3014479596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_stress_all.3014479596 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_stress_all/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac.2705745145
Short name T363
Test name
Test status
Simulation time 368623029 ps
CPU time 6.17 seconds
Started Mar 24 02:03:55 PM PDT 24
Finished Mar 24 02:04:02 PM PDT 24
Peak memory 218616 kb
Host smart-4cbac590-684f-4e12-b2ae-a67fed08b29e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705745145 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 29.kmac_test_vectors_kmac.2705745145 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_kmac_xof.4274112140
Short name T1015
Test name
Test status
Simulation time 206188459 ps
CPU time 6.3 seconds
Started Mar 24 02:03:58 PM PDT 24
Finished Mar 24 02:04:05 PM PDT 24
Peak memory 226656 kb
Host smart-850d0f27-cc62-4a43-88cb-f6050defe1a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274112140 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 29.kmac_test_vectors_kmac_xof.4274112140 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_224.2701074956
Short name T6
Test name
Test status
Simulation time 63860112000 ps
CPU time 2303.5 seconds
Started Mar 24 02:03:52 PM PDT 24
Finished Mar 24 02:42:15 PM PDT 24
Peak memory 387124 kb
Host smart-7e40941a-4ab1-4e89-b569-1479582c31e4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2701074956 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_224.2701074956 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_256.3013122327
Short name T468
Test name
Test status
Simulation time 79722064093 ps
CPU time 2140.16 seconds
Started Mar 24 02:03:50 PM PDT 24
Finished Mar 24 02:39:31 PM PDT 24
Peak memory 382960 kb
Host smart-77dea39b-d109-44c2-a301-2b0fda8d0cf1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3013122327 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_256.3013122327 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_384.790399652
Short name T315
Test name
Test status
Simulation time 204064211885 ps
CPU time 1702.81 seconds
Started Mar 24 02:03:55 PM PDT 24
Finished Mar 24 02:32:18 PM PDT 24
Peak memory 346544 kb
Host smart-e0ace119-f402-4bbe-9504-a4bc6b875dd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=790399652 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_384.790399652 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_sha3_512.1128521638
Short name T384
Test name
Test status
Simulation time 21783782727 ps
CPU time 1241.92 seconds
Started Mar 24 02:03:49 PM PDT 24
Finished Mar 24 02:24:32 PM PDT 24
Peak memory 301536 kb
Host smart-9f7ac584-d796-48ba-9ca7-5324cb41e829
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1128521638 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_sha3_512.1128521638 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_128.2049749502
Short name T952
Test name
Test status
Simulation time 248976711204 ps
CPU time 5533.08 seconds
Started Mar 24 02:03:53 PM PDT 24
Finished Mar 24 03:36:07 PM PDT 24
Peak memory 653768 kb
Host smart-51dcb266-7aa9-497f-a1b0-f031557a61f6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2049749502 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_128.2049749502 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/29.kmac_test_vectors_shake_256.671348706
Short name T1008
Test name
Test status
Simulation time 60935352494 ps
CPU time 4588.52 seconds
Started Mar 24 02:03:57 PM PDT 24
Finished Mar 24 03:20:26 PM PDT 24
Peak memory 571668 kb
Host smart-6565070d-8309-4dbb-a52a-e6016f013cfb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=671348706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_test_vectors_shake_256.671348706 +enable_masking=1 +sw_key_masked=0
Directory /workspace/29.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/3.kmac_alert_test.1704637735
Short name T626
Test name
Test status
Simulation time 20677902 ps
CPU time 0.8 seconds
Started Mar 24 01:57:50 PM PDT 24
Finished Mar 24 01:57:51 PM PDT 24
Peak memory 218796 kb
Host smart-7d7bef7f-250e-4a96-93cb-4e0c48adcded
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704637735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.1704637735 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_alert_test/latest

Test location /workspace/coverage/default/3.kmac_app.646222298
Short name T225
Test name
Test status
Simulation time 48868650065 ps
CPU time 319.56 seconds
Started Mar 24 01:57:59 PM PDT 24
Finished Mar 24 02:03:18 PM PDT 24
Peak memory 247424 kb
Host smart-63b2f3c3-93ec-42f4-a5ac-94e6f3339bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646222298 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.646222298 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app/latest

Test location /workspace/coverage/default/3.kmac_app_with_partial_data.2438477075
Short name T856
Test name
Test status
Simulation time 25532544846 ps
CPU time 212.12 seconds
Started Mar 24 01:57:49 PM PDT 24
Finished Mar 24 02:01:21 PM PDT 24
Peak memory 243592 kb
Host smart-ad38c51c-a6b9-48e9-8648-ed4a32d14ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438477075 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.2438477075 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/3.kmac_burst_write.4233356425
Short name T880
Test name
Test status
Simulation time 97738702717 ps
CPU time 731.71 seconds
Started Mar 24 01:57:47 PM PDT 24
Finished Mar 24 02:09:59 PM PDT 24
Peak memory 235536 kb
Host smart-bab2d64e-e528-4c28-ad93-c8de3483b63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233356425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.4233356425 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_burst_write/latest

Test location /workspace/coverage/default/3.kmac_edn_timeout_error.3009815398
Short name T606
Test name
Test status
Simulation time 152200580 ps
CPU time 1.2 seconds
Started Mar 24 01:57:47 PM PDT 24
Finished Mar 24 01:57:48 PM PDT 24
Peak memory 218596 kb
Host smart-822b031a-22d0-49d1-b964-c7414e83c44f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3009815398 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.3009815398 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_mode_error.2895797575
Short name T854
Test name
Test status
Simulation time 121128632 ps
CPU time 1.1 seconds
Started Mar 24 01:57:46 PM PDT 24
Finished Mar 24 01:57:48 PM PDT 24
Peak memory 222100 kb
Host smart-c6184454-f18a-4004-afe1-797094dbfdc5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2895797575 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.2895797575 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/3.kmac_entropy_refresh.3009667218
Short name T942
Test name
Test status
Simulation time 7123738964 ps
CPU time 138.42 seconds
Started Mar 24 01:57:45 PM PDT 24
Finished Mar 24 02:00:04 PM PDT 24
Peak memory 236556 kb
Host smart-de7e2515-10b2-423d-b46a-fc501095acd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009667218 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.3009667218 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/3.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/3.kmac_key_error.1980101488
Short name T310
Test name
Test status
Simulation time 2296936648 ps
CPU time 3.68 seconds
Started Mar 24 01:57:48 PM PDT 24
Finished Mar 24 01:57:52 PM PDT 24
Peak memory 218612 kb
Host smart-a93e44ce-4678-4f70-bc0c-dd2e842d281a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980101488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.1980101488 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_key_error/latest

Test location /workspace/coverage/default/3.kmac_lc_escalation.2254241377
Short name T999
Test name
Test status
Simulation time 59486009 ps
CPU time 1.34 seconds
Started Mar 24 01:57:52 PM PDT 24
Finished Mar 24 01:57:53 PM PDT 24
Peak memory 226644 kb
Host smart-f7335b81-2cc9-41a0-ac04-1118445a1a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254241377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.2254241377 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/3.kmac_lc_escalation/latest

Test location /workspace/coverage/default/3.kmac_long_msg_and_output.2945395256
Short name T104
Test name
Test status
Simulation time 72424127226 ps
CPU time 1822.57 seconds
Started Mar 24 01:57:47 PM PDT 24
Finished Mar 24 02:28:10 PM PDT 24
Peak memory 388848 kb
Host smart-902b7fb0-b7cd-46f8-aa77-efe1e2df66d1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945395256 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_an
d_output.2945395256 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/3.kmac_mubi.1120852999
Short name T1003
Test name
Test status
Simulation time 11986388950 ps
CPU time 58.13 seconds
Started Mar 24 01:57:47 PM PDT 24
Finished Mar 24 01:58:45 PM PDT 24
Peak memory 228280 kb
Host smart-b5be5e94-c0f3-4695-af12-29894e5235f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120852999 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.1120852999 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_mubi/latest

Test location /workspace/coverage/default/3.kmac_sec_cm.1548702735
Short name T82
Test name
Test status
Simulation time 9448968961 ps
CPU time 72.26 seconds
Started Mar 24 01:57:52 PM PDT 24
Finished Mar 24 01:59:04 PM PDT 24
Peak memory 264684 kb
Host smart-2ef72314-e04f-4ede-a6a5-cd1bba199f60
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548702735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.1548702735 +enable_maski
ng=1 +sw_key_masked=0
Directory /workspace/3.kmac_sec_cm/latest

Test location /workspace/coverage/default/3.kmac_sideload.3073853106
Short name T433
Test name
Test status
Simulation time 20041044827 ps
CPU time 396.87 seconds
Started Mar 24 01:57:47 PM PDT 24
Finished Mar 24 02:04:24 PM PDT 24
Peak memory 249448 kb
Host smart-84b497a0-82b2-4b8b-9979-1153c918d8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073853106 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.3073853106 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_sideload/latest

Test location /workspace/coverage/default/3.kmac_smoke.1456928399
Short name T143
Test name
Test status
Simulation time 2863917820 ps
CPU time 57.15 seconds
Started Mar 24 01:57:59 PM PDT 24
Finished Mar 24 01:58:56 PM PDT 24
Peak memory 226764 kb
Host smart-d29ba8b2-2e75-41a8-9157-7bf5a6e94d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456928399 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.1456928399 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_smoke/latest

Test location /workspace/coverage/default/3.kmac_stress_all.2559923794
Short name T935
Test name
Test status
Simulation time 26043313382 ps
CPU time 984.39 seconds
Started Mar 24 01:57:51 PM PDT 24
Finished Mar 24 02:14:16 PM PDT 24
Peak memory 308504 kb
Host smart-47800d82-4e90-4332-81f1-5e98ccae885b
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2559923794 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all.2559923794 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all/latest

Test location /workspace/coverage/default/3.kmac_stress_all_with_rand_reset.2116991788
Short name T120
Test name
Test status
Simulation time 58491519102 ps
CPU time 962.86 seconds
Started Mar 24 01:57:53 PM PDT 24
Finished Mar 24 02:13:56 PM PDT 24
Peak memory 276500 kb
Host smart-f7edb2e7-0034-4413-b428-0a472715e81e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2116991788 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_rand_reset.2116991788 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac.2880082528
Short name T1041
Test name
Test status
Simulation time 465624109 ps
CPU time 5.43 seconds
Started Mar 24 01:57:46 PM PDT 24
Finished Mar 24 01:57:52 PM PDT 24
Peak memory 226796 kb
Host smart-89247644-3374-40ce-b46e-88cde50e426c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880082528 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 3.kmac_test_vectors_kmac.2880082528 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_kmac_xof.3864348477
Short name T983
Test name
Test status
Simulation time 508444566 ps
CPU time 6.33 seconds
Started Mar 24 01:57:47 PM PDT 24
Finished Mar 24 01:57:53 PM PDT 24
Peak memory 218652 kb
Host smart-38247266-452d-4e07-82c9-5d837aebea9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864348477 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 3.kmac_test_vectors_kmac_xof.3864348477 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_224.204632595
Short name T213
Test name
Test status
Simulation time 538803902971 ps
CPU time 2549.6 seconds
Started Mar 24 01:57:58 PM PDT 24
Finished Mar 24 02:40:28 PM PDT 24
Peak memory 395232 kb
Host smart-8848d6c4-3849-4542-9478-c3716ab84530
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=204632595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.204632595 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_256.950275979
Short name T530
Test name
Test status
Simulation time 19206097641 ps
CPU time 1840.24 seconds
Started Mar 24 01:57:46 PM PDT 24
Finished Mar 24 02:28:27 PM PDT 24
Peak memory 387632 kb
Host smart-8dae81cc-dbc7-4030-8b28-c87bd3c6e076
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=950275979 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.950275979 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_384.2857649236
Short name T5
Test name
Test status
Simulation time 31408136551 ps
CPU time 1468.5 seconds
Started Mar 24 01:57:47 PM PDT 24
Finished Mar 24 02:22:15 PM PDT 24
Peak memory 334652 kb
Host smart-981942e2-d84b-4818-ba41-e96489b58762
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2857649236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.2857649236 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_sha3_512.3473935555
Short name T656
Test name
Test status
Simulation time 48790895513 ps
CPU time 1285.62 seconds
Started Mar 24 01:57:45 PM PDT 24
Finished Mar 24 02:19:11 PM PDT 24
Peak memory 296540 kb
Host smart-80d367c7-f195-4322-8a5a-c864f8e6c5e0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3473935555 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.3473935555 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_128.4291812144
Short name T253
Test name
Test status
Simulation time 154914187719 ps
CPU time 5229.37 seconds
Started Mar 24 01:57:59 PM PDT 24
Finished Mar 24 03:25:09 PM PDT 24
Peak memory 653416 kb
Host smart-4d7e3ad1-da7c-4661-82b7-805cc7158cbd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4291812144 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.4291812144 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/3.kmac_test_vectors_shake_256.2247884705
Short name T815
Test name
Test status
Simulation time 70399257393 ps
CPU time 4478.34 seconds
Started Mar 24 01:57:58 PM PDT 24
Finished Mar 24 03:12:37 PM PDT 24
Peak memory 573776 kb
Host smart-b42e34ed-50c3-452a-aebd-7f570f727e5c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2247884705 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.2247884705 +enable_masking=1 +sw_key_masked=0
Directory /workspace/3.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/30.kmac_alert_test.864034629
Short name T654
Test name
Test status
Simulation time 17945142 ps
CPU time 0.85 seconds
Started Mar 24 02:04:27 PM PDT 24
Finished Mar 24 02:04:29 PM PDT 24
Peak memory 218488 kb
Host smart-1c635997-aaab-49e9-b400-3ecd9f418efe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864034629 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_alert_test.864034629 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/30.kmac_alert_test/latest

Test location /workspace/coverage/default/30.kmac_app.135962980
Short name T457
Test name
Test status
Simulation time 15030988846 ps
CPU time 273.91 seconds
Started Mar 24 02:04:21 PM PDT 24
Finished Mar 24 02:08:55 PM PDT 24
Peak memory 247760 kb
Host smart-a1473aaf-41fa-4a23-a256-a9c69335eb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=135962980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_app.135962980 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_app/latest

Test location /workspace/coverage/default/30.kmac_burst_write.2073436605
Short name T369
Test name
Test status
Simulation time 8578661545 ps
CPU time 864.99 seconds
Started Mar 24 02:04:11 PM PDT 24
Finished Mar 24 02:18:36 PM PDT 24
Peak memory 237056 kb
Host smart-07ad40f4-70fc-4274-bafe-856f39e1bd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073436605 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_burst_write.2073436605 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_burst_write/latest

Test location /workspace/coverage/default/30.kmac_entropy_refresh.1441428689
Short name T281
Test name
Test status
Simulation time 1711874553 ps
CPU time 51.29 seconds
Started Mar 24 02:04:21 PM PDT 24
Finished Mar 24 02:05:12 PM PDT 24
Peak memory 236164 kb
Host smart-f2015442-c3dd-4e1b-a1f4-1e4a3caf6560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441428689 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_entropy_refresh.1441428689 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/30.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/30.kmac_error.3887252515
Short name T155
Test name
Test status
Simulation time 57279093421 ps
CPU time 510.33 seconds
Started Mar 24 02:04:22 PM PDT 24
Finished Mar 24 02:12:53 PM PDT 24
Peak memory 259580 kb
Host smart-8a32e777-fcc6-46ff-9611-2841c00a43ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887252515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_error.3887252515 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_error/latest

Test location /workspace/coverage/default/30.kmac_key_error.2200255644
Short name T443
Test name
Test status
Simulation time 4362792520 ps
CPU time 5.02 seconds
Started Mar 24 02:04:21 PM PDT 24
Finished Mar 24 02:04:26 PM PDT 24
Peak memory 218576 kb
Host smart-5e83aa49-5e59-475c-968a-810ef37315eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200255644 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_key_error.2200255644 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_key_error/latest

Test location /workspace/coverage/default/30.kmac_lc_escalation.4161648373
Short name T24
Test name
Test status
Simulation time 294326979 ps
CPU time 1.48 seconds
Started Mar 24 02:04:20 PM PDT 24
Finished Mar 24 02:04:22 PM PDT 24
Peak memory 218600 kb
Host smart-e81e17e5-1661-4c14-978b-04752c0f2d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161648373 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.4161648373 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/30.kmac_lc_escalation/latest

Test location /workspace/coverage/default/30.kmac_long_msg_and_output.4058306397
Short name T619
Test name
Test status
Simulation time 57470148382 ps
CPU time 2049.03 seconds
Started Mar 24 02:04:13 PM PDT 24
Finished Mar 24 02:38:24 PM PDT 24
Peak memory 386976 kb
Host smart-ae73b0ff-bce9-4fe1-8186-e838ee7df2ba
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058306397 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_long_msg_a
nd_output.4058306397 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/30.kmac_sideload.1550037639
Short name T334
Test name
Test status
Simulation time 30266753209 ps
CPU time 486.83 seconds
Started Mar 24 02:04:13 PM PDT 24
Finished Mar 24 02:12:21 PM PDT 24
Peak memory 255488 kb
Host smart-3dbe9558-b9aa-45ef-855c-5b09a6f5450a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550037639 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload.1550037639 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_sideload/latest

Test location /workspace/coverage/default/30.kmac_smoke.1242477504
Short name T807
Test name
Test status
Simulation time 4911025672 ps
CPU time 60.79 seconds
Started Mar 24 02:04:13 PM PDT 24
Finished Mar 24 02:05:15 PM PDT 24
Peak memory 222028 kb
Host smart-c1c3875a-e9de-4a29-8db4-22988123f667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242477504 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_smoke.1242477504 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_smoke/latest

Test location /workspace/coverage/default/30.kmac_stress_all.209759434
Short name T776
Test name
Test status
Simulation time 56613008846 ps
CPU time 481.83 seconds
Started Mar 24 02:04:29 PM PDT 24
Finished Mar 24 02:12:31 PM PDT 24
Peak memory 285296 kb
Host smart-695ee0d8-59ea-4d13-8d3f-bf14e51141a8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=209759434 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_stress_all.209759434 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_stress_all/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac.2218256169
Short name T786
Test name
Test status
Simulation time 401966129 ps
CPU time 5.77 seconds
Started Mar 24 02:04:20 PM PDT 24
Finished Mar 24 02:04:26 PM PDT 24
Peak memory 226720 kb
Host smart-7c7bb681-f3ed-40b4-883c-e63205ada0d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218256169 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 30.kmac_test_vectors_kmac.2218256169 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_kmac_xof.3120354836
Short name T304
Test name
Test status
Simulation time 438619598 ps
CPU time 6.29 seconds
Started Mar 24 02:04:20 PM PDT 24
Finished Mar 24 02:04:27 PM PDT 24
Peak memory 226588 kb
Host smart-9d2b091f-695e-4945-a3ea-4ac950847729
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120354836 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 30.kmac_test_vectors_kmac_xof.3120354836 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_224.3630955932
Short name T359
Test name
Test status
Simulation time 295475946368 ps
CPU time 2108.1 seconds
Started Mar 24 02:04:15 PM PDT 24
Finished Mar 24 02:39:24 PM PDT 24
Peak memory 403684 kb
Host smart-e34bf0f2-eb44-42db-bf37-236ca3367fb9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3630955932 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_224.3630955932 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_256.4292531617
Short name T293
Test name
Test status
Simulation time 92918704224 ps
CPU time 2057.7 seconds
Started Mar 24 02:04:16 PM PDT 24
Finished Mar 24 02:38:35 PM PDT 24
Peak memory 374456 kb
Host smart-69f62997-9534-45fa-9d25-8220b0c05d64
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4292531617 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_256.4292531617 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_384.2243576558
Short name T871
Test name
Test status
Simulation time 38501980269 ps
CPU time 1488.1 seconds
Started Mar 24 02:04:18 PM PDT 24
Finished Mar 24 02:29:06 PM PDT 24
Peak memory 341300 kb
Host smart-3267a421-2a67-4869-a6ad-594dd27dc06c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2243576558 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_384.2243576558 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_sha3_512.705528522
Short name T187
Test name
Test status
Simulation time 140076737079 ps
CPU time 1263.13 seconds
Started Mar 24 02:04:18 PM PDT 24
Finished Mar 24 02:25:21 PM PDT 24
Peak memory 303520 kb
Host smart-568f26a5-75b2-46fd-96b5-3ff24670763a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=705528522 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_sha3_512.705528522 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_128.2263724211
Short name T198
Test name
Test status
Simulation time 242181332819 ps
CPU time 5336.99 seconds
Started Mar 24 02:04:15 PM PDT 24
Finished Mar 24 03:33:13 PM PDT 24
Peak memory 654148 kb
Host smart-af9c4f13-e056-42cd-a3d0-edce45a0b8eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2263724211 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_128.2263724211 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/30.kmac_test_vectors_shake_256.2213831212
Short name T1060
Test name
Test status
Simulation time 78056789742 ps
CPU time 4257.95 seconds
Started Mar 24 02:04:21 PM PDT 24
Finished Mar 24 03:15:19 PM PDT 24
Peak memory 573676 kb
Host smart-2486cead-9bf5-4494-87c0-67fc952e9e79
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2213831212 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_test_vectors_shake_256.2213831212 +enable_masking=1 +sw_key_masked=0
Directory /workspace/30.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/31.kmac_alert_test.4114175101
Short name T832
Test name
Test status
Simulation time 25463490 ps
CPU time 0.86 seconds
Started Mar 24 02:04:46 PM PDT 24
Finished Mar 24 02:04:48 PM PDT 24
Peak memory 218376 kb
Host smart-6274bc4e-4ee6-4c13-b32a-576ffe0771b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114175101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_alert_test.4114175101 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_alert_test/latest

Test location /workspace/coverage/default/31.kmac_app.1652798029
Short name T521
Test name
Test status
Simulation time 3173697905 ps
CPU time 25.07 seconds
Started Mar 24 02:04:42 PM PDT 24
Finished Mar 24 02:05:07 PM PDT 24
Peak memory 224192 kb
Host smart-f913d503-d862-4068-871c-cdda1bef8407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652798029 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_app.1652798029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_app/latest

Test location /workspace/coverage/default/31.kmac_burst_write.111267885
Short name T409
Test name
Test status
Simulation time 28034071708 ps
CPU time 715.27 seconds
Started Mar 24 02:04:33 PM PDT 24
Finished Mar 24 02:16:29 PM PDT 24
Peak memory 235588 kb
Host smart-36362ef4-528b-461f-97d6-57f0d018527b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111267885 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_burst_write.111267885 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_burst_write/latest

Test location /workspace/coverage/default/31.kmac_entropy_refresh.3683819936
Short name T503
Test name
Test status
Simulation time 372876938 ps
CPU time 14.24 seconds
Started Mar 24 02:04:42 PM PDT 24
Finished Mar 24 02:04:57 PM PDT 24
Peak memory 226772 kb
Host smart-57384eb1-fbe9-41d5-8909-c4985f4c1092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683819936 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_entropy_refresh.3683819936 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/31.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/31.kmac_error.1479433835
Short name T1047
Test name
Test status
Simulation time 53077545981 ps
CPU time 330.56 seconds
Started Mar 24 02:04:42 PM PDT 24
Finished Mar 24 02:10:14 PM PDT 24
Peak memory 256632 kb
Host smart-2177d3b7-ed84-494b-8c3e-6ef22ec8d84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479433835 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_error.1479433835 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_error/latest

Test location /workspace/coverage/default/31.kmac_key_error.2363853561
Short name T541
Test name
Test status
Simulation time 5275082090 ps
CPU time 4.93 seconds
Started Mar 24 02:04:47 PM PDT 24
Finished Mar 24 02:04:52 PM PDT 24
Peak memory 218568 kb
Host smart-17d7f841-85ed-4cd0-b52f-6da5cb4f850f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363853561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_key_error.2363853561 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_key_error/latest

Test location /workspace/coverage/default/31.kmac_lc_escalation.2701432174
Short name T1066
Test name
Test status
Simulation time 71293589 ps
CPU time 1.51 seconds
Started Mar 24 02:04:50 PM PDT 24
Finished Mar 24 02:04:54 PM PDT 24
Peak memory 218640 kb
Host smart-8263880f-5cd1-4336-8c1f-48854a637af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701432174 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.2701432174 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/31.kmac_lc_escalation/latest

Test location /workspace/coverage/default/31.kmac_long_msg_and_output.4085993019
Short name T649
Test name
Test status
Simulation time 33324429360 ps
CPU time 1807.73 seconds
Started Mar 24 02:04:34 PM PDT 24
Finished Mar 24 02:34:43 PM PDT 24
Peak memory 380420 kb
Host smart-6ca80bae-a109-4cca-8aff-9bb4261a50e1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085993019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_long_msg_a
nd_output.4085993019 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/31.kmac_sideload.2378308249
Short name T1027
Test name
Test status
Simulation time 5783571845 ps
CPU time 433.58 seconds
Started Mar 24 02:04:33 PM PDT 24
Finished Mar 24 02:11:47 PM PDT 24
Peak memory 255240 kb
Host smart-32b0cbcd-789d-4a1f-8181-ad093779840c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378308249 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload.2378308249 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_sideload/latest

Test location /workspace/coverage/default/31.kmac_smoke.4011860460
Short name T696
Test name
Test status
Simulation time 6196976821 ps
CPU time 37.56 seconds
Started Mar 24 02:04:32 PM PDT 24
Finished Mar 24 02:05:10 PM PDT 24
Peak memory 226688 kb
Host smart-6d1437b6-35ae-414c-a3e4-e7e969e7e4b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011860460 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_smoke.4011860460 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_smoke/latest

Test location /workspace/coverage/default/31.kmac_stress_all.1331373206
Short name T476
Test name
Test status
Simulation time 46068728312 ps
CPU time 689.25 seconds
Started Mar 24 02:04:47 PM PDT 24
Finished Mar 24 02:16:17 PM PDT 24
Peak memory 282828 kb
Host smart-2d7f8784-35dc-4665-8b5f-8cd1d9d65469
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1331373206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_stress_all.1331373206 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_stress_all/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac.1164274301
Short name T793
Test name
Test status
Simulation time 134931506 ps
CPU time 6.54 seconds
Started Mar 24 02:04:42 PM PDT 24
Finished Mar 24 02:04:50 PM PDT 24
Peak memory 218652 kb
Host smart-fd0710aa-7b35-4fdf-a5b3-abe3e0a6b63b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164274301 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 31.kmac_test_vectors_kmac.1164274301 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_kmac_xof.393676820
Short name T835
Test name
Test status
Simulation time 963486952 ps
CPU time 6.87 seconds
Started Mar 24 02:04:42 PM PDT 24
Finished Mar 24 02:04:50 PM PDT 24
Peak memory 226660 kb
Host smart-f3edede4-ebb0-4ff9-bb17-920c0fc14200
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393676820 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 31.kmac_test_vectors_kmac_xof.393676820 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_224.3346409453
Short name T587
Test name
Test status
Simulation time 27795520689 ps
CPU time 1908.43 seconds
Started Mar 24 02:04:37 PM PDT 24
Finished Mar 24 02:36:26 PM PDT 24
Peak memory 391032 kb
Host smart-5e995c1c-ac46-415c-9ebd-ba1a0c8f5ff1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3346409453 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_224.3346409453 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_256.3727596042
Short name T1071
Test name
Test status
Simulation time 189694396214 ps
CPU time 1779.96 seconds
Started Mar 24 02:04:40 PM PDT 24
Finished Mar 24 02:34:21 PM PDT 24
Peak memory 383480 kb
Host smart-4874b4eb-e4ed-45c6-8d10-720defc0c216
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3727596042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_256.3727596042 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_384.3529586333
Short name T439
Test name
Test status
Simulation time 63333572477 ps
CPU time 1548.94 seconds
Started Mar 24 02:04:41 PM PDT 24
Finished Mar 24 02:30:30 PM PDT 24
Peak memory 340112 kb
Host smart-48104f65-2e51-4260-8aac-6d1d8f42d7dd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3529586333 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_384.3529586333 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_sha3_512.1065915777
Short name T610
Test name
Test status
Simulation time 10882933591 ps
CPU time 1198.86 seconds
Started Mar 24 02:04:40 PM PDT 24
Finished Mar 24 02:24:40 PM PDT 24
Peak memory 300200 kb
Host smart-003706ad-bb77-4d88-9889-a57c28d42b52
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1065915777 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_sha3_512.1065915777 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_128.1217591488
Short name T722
Test name
Test status
Simulation time 236875458058 ps
CPU time 5951.54 seconds
Started Mar 24 02:04:38 PM PDT 24
Finished Mar 24 03:43:50 PM PDT 24
Peak memory 649644 kb
Host smart-9db3ea9a-2eb7-4f50-b032-8d939cff4d4c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1217591488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_128.1217591488 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/31.kmac_test_vectors_shake_256.4211846037
Short name T400
Test name
Test status
Simulation time 620224743860 ps
CPU time 5309.34 seconds
Started Mar 24 02:04:42 PM PDT 24
Finished Mar 24 03:33:12 PM PDT 24
Peak memory 567028 kb
Host smart-5490bf1e-4f26-4723-bffc-07b282c28734
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4211846037 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_test_vectors_shake_256.4211846037 +enable_masking=1 +sw_key_masked=0
Directory /workspace/31.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/32.kmac_alert_test.2907203206
Short name T687
Test name
Test status
Simulation time 26093639 ps
CPU time 0.85 seconds
Started Mar 24 02:05:06 PM PDT 24
Finished Mar 24 02:05:07 PM PDT 24
Peak memory 218468 kb
Host smart-1da8c1f4-4891-4291-94db-16192dbf23e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907203206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_alert_test.2907203206 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_alert_test/latest

Test location /workspace/coverage/default/32.kmac_app.3291220560
Short name T460
Test name
Test status
Simulation time 4288825870 ps
CPU time 57.65 seconds
Started Mar 24 02:05:00 PM PDT 24
Finished Mar 24 02:05:58 PM PDT 24
Peak memory 229432 kb
Host smart-a2b2141e-00c2-4772-8a7d-78c834cea034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291220560 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_app.3291220560 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_app/latest

Test location /workspace/coverage/default/32.kmac_burst_write.1884498972
Short name T612
Test name
Test status
Simulation time 3252902254 ps
CPU time 127.81 seconds
Started Mar 24 02:04:48 PM PDT 24
Finished Mar 24 02:06:57 PM PDT 24
Peak memory 226388 kb
Host smart-5c0a2553-a197-4507-be1a-1b92f0f6af22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884498972 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_burst_write.1884498972 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_burst_write/latest

Test location /workspace/coverage/default/32.kmac_entropy_refresh.3553445306
Short name T68
Test name
Test status
Simulation time 23503573095 ps
CPU time 299.37 seconds
Started Mar 24 02:05:01 PM PDT 24
Finished Mar 24 02:10:00 PM PDT 24
Peak memory 247696 kb
Host smart-8b708ddc-69f3-4fcd-b8c8-600962e6e38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553445306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_entropy_refresh.3553445306 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/32.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/32.kmac_error.2475789315
Short name T505
Test name
Test status
Simulation time 26035918276 ps
CPU time 324.73 seconds
Started Mar 24 02:05:00 PM PDT 24
Finished Mar 24 02:10:25 PM PDT 24
Peak memory 252264 kb
Host smart-82fa493a-f95a-43e3-b20b-045dee6039e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475789315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_error.2475789315 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_error/latest

Test location /workspace/coverage/default/32.kmac_key_error.1107924706
Short name T730
Test name
Test status
Simulation time 752184765 ps
CPU time 2.7 seconds
Started Mar 24 02:05:02 PM PDT 24
Finished Mar 24 02:05:05 PM PDT 24
Peak memory 218560 kb
Host smart-fcc252ef-828e-42db-97a4-e03753722135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107924706 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_key_error.1107924706 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_key_error/latest

Test location /workspace/coverage/default/32.kmac_lc_escalation.2922693371
Short name T79
Test name
Test status
Simulation time 33314809 ps
CPU time 1.43 seconds
Started Mar 24 02:05:01 PM PDT 24
Finished Mar 24 02:05:03 PM PDT 24
Peak memory 218604 kb
Host smart-1dc32080-cd3b-4736-94ac-4405353a95ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922693371 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.2922693371 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/32.kmac_lc_escalation/latest

Test location /workspace/coverage/default/32.kmac_long_msg_and_output.2758868943
Short name T492
Test name
Test status
Simulation time 11266525446 ps
CPU time 307.32 seconds
Started Mar 24 02:04:47 PM PDT 24
Finished Mar 24 02:09:55 PM PDT 24
Peak memory 245068 kb
Host smart-663b9712-0baf-4b16-af54-e0846fc51854
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758868943 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_long_msg_a
nd_output.2758868943 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/32.kmac_sideload.3895059452
Short name T977
Test name
Test status
Simulation time 3450417685 ps
CPU time 117.73 seconds
Started Mar 24 02:04:48 PM PDT 24
Finished Mar 24 02:06:47 PM PDT 24
Peak memory 233132 kb
Host smart-0bbbc1d1-2e5c-4f61-a98c-386113ee75a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895059452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload.3895059452 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_sideload/latest

Test location /workspace/coverage/default/32.kmac_smoke.3978673511
Short name T275
Test name
Test status
Simulation time 4196305803 ps
CPU time 66.01 seconds
Started Mar 24 02:04:47 PM PDT 24
Finished Mar 24 02:05:53 PM PDT 24
Peak memory 222572 kb
Host smart-44836c9b-e4c2-4772-ad54-4385d6e6f138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978673511 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_smoke.3978673511 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_smoke/latest

Test location /workspace/coverage/default/32.kmac_stress_all.3899382153
Short name T43
Test name
Test status
Simulation time 217728585727 ps
CPU time 1513.85 seconds
Started Mar 24 02:05:01 PM PDT 24
Finished Mar 24 02:30:16 PM PDT 24
Peak memory 373824 kb
Host smart-773a9147-a762-469e-b773-10602f9b668e
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3899382153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_stress_all.3899382153 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_stress_all/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac.3360431029
Short name T108
Test name
Test status
Simulation time 581066156 ps
CPU time 5.93 seconds
Started Mar 24 02:04:57 PM PDT 24
Finished Mar 24 02:05:03 PM PDT 24
Peak memory 218608 kb
Host smart-622c5662-7a99-4fc7-b1fe-2a8b5db2fe53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360431029 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 32.kmac_test_vectors_kmac.3360431029 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_kmac_xof.2647516542
Short name T986
Test name
Test status
Simulation time 871877807 ps
CPU time 6.13 seconds
Started Mar 24 02:04:55 PM PDT 24
Finished Mar 24 02:05:02 PM PDT 24
Peak memory 226728 kb
Host smart-c265a7b1-82cb-46a4-9e78-5687bd5644ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647516542 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 32.kmac_test_vectors_kmac_xof.2647516542 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_224.2087799243
Short name T234
Test name
Test status
Simulation time 31920049482 ps
CPU time 2183.2 seconds
Started Mar 24 02:04:47 PM PDT 24
Finished Mar 24 02:41:11 PM PDT 24
Peak memory 398332 kb
Host smart-a99734e5-fb98-4065-a550-42d50e5d510a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2087799243 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_224.2087799243 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_256.383504176
Short name T659
Test name
Test status
Simulation time 65394695983 ps
CPU time 2264.46 seconds
Started Mar 24 02:04:50 PM PDT 24
Finished Mar 24 02:42:37 PM PDT 24
Peak memory 388116 kb
Host smart-4cf754f9-cc4b-4be9-bde8-9c6dd53fa757
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=383504176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_256.383504176 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_384.4032006707
Short name T206
Test name
Test status
Simulation time 50255007802 ps
CPU time 1644.06 seconds
Started Mar 24 02:04:55 PM PDT 24
Finished Mar 24 02:32:20 PM PDT 24
Peak memory 342576 kb
Host smart-8e179c6e-b5aa-46ab-a6c2-b8e71025bb5d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4032006707 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_384.4032006707 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_sha3_512.1468648321
Short name T945
Test name
Test status
Simulation time 14273581017 ps
CPU time 1121.01 seconds
Started Mar 24 02:04:55 PM PDT 24
Finished Mar 24 02:23:37 PM PDT 24
Peak memory 300056 kb
Host smart-b8a73614-81e3-49fa-a864-46a8367bfc6e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1468648321 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_sha3_512.1468648321 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_128.3521961002
Short name T364
Test name
Test status
Simulation time 765608958442 ps
CPU time 5715.08 seconds
Started Mar 24 02:04:55 PM PDT 24
Finished Mar 24 03:40:12 PM PDT 24
Peak memory 642240 kb
Host smart-25732074-6ca8-4846-b5ae-ed335701dc7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3521961002 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_128.3521961002 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/32.kmac_test_vectors_shake_256.3778824110
Short name T232
Test name
Test status
Simulation time 54554054590 ps
CPU time 4591.4 seconds
Started Mar 24 02:04:57 PM PDT 24
Finished Mar 24 03:21:30 PM PDT 24
Peak memory 572992 kb
Host smart-c0e03efc-a3fa-4d8a-9835-3447c027c037
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3778824110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_test_vectors_shake_256.3778824110 +enable_masking=1 +sw_key_masked=0
Directory /workspace/32.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/33.kmac_alert_test.2338051987
Short name T361
Test name
Test status
Simulation time 20171113 ps
CPU time 0.87 seconds
Started Mar 24 02:05:34 PM PDT 24
Finished Mar 24 02:05:35 PM PDT 24
Peak memory 218472 kb
Host smart-9a0b1a23-ee18-495d-81ad-7b5d020f99bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338051987 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_alert_test.2338051987 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_alert_test/latest

Test location /workspace/coverage/default/33.kmac_app.340207030
Short name T1062
Test name
Test status
Simulation time 17762861845 ps
CPU time 126.27 seconds
Started Mar 24 02:05:25 PM PDT 24
Finished Mar 24 02:07:31 PM PDT 24
Peak memory 235368 kb
Host smart-13d3375d-df14-4666-81dc-73ebd9950c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340207030 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_app.340207030 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_app/latest

Test location /workspace/coverage/default/33.kmac_burst_write.1786275486
Short name T9
Test name
Test status
Simulation time 23085012723 ps
CPU time 1243.03 seconds
Started Mar 24 02:05:10 PM PDT 24
Finished Mar 24 02:25:53 PM PDT 24
Peak memory 238616 kb
Host smart-10aa0da1-6a29-41d7-a7c2-057f8c512642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786275486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_burst_write.1786275486 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_burst_write/latest

Test location /workspace/coverage/default/33.kmac_entropy_refresh.3633761596
Short name T668
Test name
Test status
Simulation time 15709831792 ps
CPU time 353.06 seconds
Started Mar 24 02:05:23 PM PDT 24
Finished Mar 24 02:11:16 PM PDT 24
Peak memory 248032 kb
Host smart-8043ad37-33b1-421a-8017-2140b0401247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633761596 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_entropy_refresh.3633761596 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/33.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/33.kmac_error.2046635525
Short name T876
Test name
Test status
Simulation time 170203394105 ps
CPU time 307.4 seconds
Started Mar 24 02:05:24 PM PDT 24
Finished Mar 24 02:10:31 PM PDT 24
Peak memory 257408 kb
Host smart-2a1663f6-6110-4410-b7e7-76047bc6eaf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046635525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_error.2046635525 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_error/latest

Test location /workspace/coverage/default/33.kmac_key_error.3366663120
Short name T394
Test name
Test status
Simulation time 949063659 ps
CPU time 5.16 seconds
Started Mar 24 02:05:24 PM PDT 24
Finished Mar 24 02:05:29 PM PDT 24
Peak memory 222288 kb
Host smart-89b4f4f0-bc0c-4d9e-a744-116336cbca85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366663120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_key_error.3366663120 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_key_error/latest

Test location /workspace/coverage/default/33.kmac_lc_escalation.5638852
Short name T509
Test name
Test status
Simulation time 100419256 ps
CPU time 1.27 seconds
Started Mar 24 02:05:28 PM PDT 24
Finished Mar 24 02:05:29 PM PDT 24
Peak memory 218612 kb
Host smart-0e56a84f-a065-4a76-9030-ff351d705d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5638852 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.5638852 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_lc_escalation/latest

Test location /workspace/coverage/default/33.kmac_long_msg_and_output.1763634072
Short name T4
Test name
Test status
Simulation time 34780731649 ps
CPU time 1768.03 seconds
Started Mar 24 02:05:07 PM PDT 24
Finished Mar 24 02:34:35 PM PDT 24
Peak memory 384364 kb
Host smart-91f65a79-0790-435f-8132-1a38047df1a2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763634072 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_long_msg_a
nd_output.1763634072 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/33.kmac_sideload.916250175
Short name T401
Test name
Test status
Simulation time 95860632063 ps
CPU time 496.63 seconds
Started Mar 24 02:05:04 PM PDT 24
Finished Mar 24 02:13:21 PM PDT 24
Peak memory 253288 kb
Host smart-22a99ab7-b4c4-489c-ac75-43b36332d10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916250175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload.916250175 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_sideload/latest

Test location /workspace/coverage/default/33.kmac_smoke.3946143980
Short name T489
Test name
Test status
Simulation time 3711968771 ps
CPU time 81.05 seconds
Started Mar 24 02:05:07 PM PDT 24
Finished Mar 24 02:06:28 PM PDT 24
Peak memory 226788 kb
Host smart-522b949f-3d2b-4bb1-b8c2-7857c51c333e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946143980 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_smoke.3946143980 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_smoke/latest

Test location /workspace/coverage/default/33.kmac_stress_all.4024675444
Short name T1035
Test name
Test status
Simulation time 35562565168 ps
CPU time 916.77 seconds
Started Mar 24 02:05:28 PM PDT 24
Finished Mar 24 02:20:45 PM PDT 24
Peak memory 300488 kb
Host smart-6f7799b2-f355-4e2e-853b-e01cda4f00b5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4024675444 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all.4024675444 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all/latest

Test location /workspace/coverage/default/33.kmac_stress_all_with_rand_reset.1510799635
Short name T41
Test name
Test status
Simulation time 79195509434 ps
CPU time 1465.4 seconds
Started Mar 24 02:05:27 PM PDT 24
Finished Mar 24 02:29:53 PM PDT 24
Peak memory 307904 kb
Host smart-3ed5acb8-6232-476e-bdd5-af3b77bee188
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1510799635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_stress_all_with_rand_reset.1510799635 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac.1564935861
Short name T283
Test name
Test status
Simulation time 1289336406 ps
CPU time 7.22 seconds
Started Mar 24 02:05:19 PM PDT 24
Finished Mar 24 02:05:26 PM PDT 24
Peak memory 226712 kb
Host smart-e26e6f79-98e0-41a5-99cf-d3e83cab62c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1564935861 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 33.kmac_test_vectors_kmac.1564935861 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_kmac_xof.1567613053
Short name T479
Test name
Test status
Simulation time 257307415 ps
CPU time 6.65 seconds
Started Mar 24 02:05:25 PM PDT 24
Finished Mar 24 02:05:31 PM PDT 24
Peak memory 226684 kb
Host smart-8f6e87ff-4aa5-4302-aa47-62d6c8c909d8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1567613053 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 33.kmac_test_vectors_kmac_xof.1567613053 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_224.1502119753
Short name T318
Test name
Test status
Simulation time 21654685682 ps
CPU time 1864.52 seconds
Started Mar 24 02:05:15 PM PDT 24
Finished Mar 24 02:36:20 PM PDT 24
Peak memory 390708 kb
Host smart-fed8cd74-25e5-4283-abb4-f8d15403b997
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1502119753 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_224.1502119753 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_256.1036300722
Short name T513
Test name
Test status
Simulation time 19354478810 ps
CPU time 1735.35 seconds
Started Mar 24 02:05:14 PM PDT 24
Finished Mar 24 02:34:09 PM PDT 24
Peak memory 387496 kb
Host smart-ef7c48fc-5cd1-4f5e-9f82-0a1595b72eb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1036300722 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_256.1036300722 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_384.3784861565
Short name T294
Test name
Test status
Simulation time 65816047975 ps
CPU time 1618.72 seconds
Started Mar 24 02:05:14 PM PDT 24
Finished Mar 24 02:32:13 PM PDT 24
Peak memory 343284 kb
Host smart-ef5d5280-cd73-4af8-8d5d-65a1092e441e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3784861565 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_384.3784861565 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_sha3_512.1705373737
Short name T651
Test name
Test status
Simulation time 10671295474 ps
CPU time 1088.19 seconds
Started Mar 24 02:05:14 PM PDT 24
Finished Mar 24 02:23:23 PM PDT 24
Peak memory 302196 kb
Host smart-139eebc5-2e26-45cc-bdb3-b8681cd9daa9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1705373737 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_sha3_512.1705373737 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_128.2859118807
Short name T829
Test name
Test status
Simulation time 132382089687 ps
CPU time 4702.86 seconds
Started Mar 24 02:05:20 PM PDT 24
Finished Mar 24 03:23:43 PM PDT 24
Peak memory 645912 kb
Host smart-04b9bf53-9888-4ffb-99ae-44a995a4f320
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2859118807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_128.2859118807 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/33.kmac_test_vectors_shake_256.1229532658
Short name T1013
Test name
Test status
Simulation time 104997090115 ps
CPU time 4565.42 seconds
Started Mar 24 02:05:20 PM PDT 24
Finished Mar 24 03:21:26 PM PDT 24
Peak memory 566792 kb
Host smart-1e903b88-e9ce-4e55-b2d4-124be48b6580
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1229532658 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_test_vectors_shake_256.1229532658 +enable_masking=1 +sw_key_masked=0
Directory /workspace/33.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/34.kmac_alert_test.4217982396
Short name T438
Test name
Test status
Simulation time 31232853 ps
CPU time 0.86 seconds
Started Mar 24 02:05:42 PM PDT 24
Finished Mar 24 02:05:43 PM PDT 24
Peak memory 218468 kb
Host smart-a75eb13f-4a30-4040-9b52-1436a4de8fc6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217982396 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_alert_test.4217982396 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_alert_test/latest

Test location /workspace/coverage/default/34.kmac_app.363000918
Short name T551
Test name
Test status
Simulation time 36669008117 ps
CPU time 310.93 seconds
Started Mar 24 02:05:38 PM PDT 24
Finished Mar 24 02:10:49 PM PDT 24
Peak memory 246424 kb
Host smart-9c43a8a9-986e-45d8-b72e-c1ed3a42def7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363000918 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_app.363000918 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_app/latest

Test location /workspace/coverage/default/34.kmac_burst_write.3057126041
Short name T10
Test name
Test status
Simulation time 32257154844 ps
CPU time 1590.7 seconds
Started Mar 24 02:05:32 PM PDT 24
Finished Mar 24 02:32:03 PM PDT 24
Peak memory 238912 kb
Host smart-ecbe42bf-f4d6-4f9b-9cea-0bb4c966d1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057126041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_burst_write.3057126041 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_burst_write/latest

Test location /workspace/coverage/default/34.kmac_entropy_refresh.2322784288
Short name T1019
Test name
Test status
Simulation time 3713995334 ps
CPU time 76 seconds
Started Mar 24 02:05:40 PM PDT 24
Finished Mar 24 02:06:56 PM PDT 24
Peak memory 229336 kb
Host smart-0989ebc6-8ccd-4d5c-9368-9a55d78c7b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322784288 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_entropy_refresh.2322784288 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/34.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/34.kmac_error.54009422
Short name T1075
Test name
Test status
Simulation time 169360900449 ps
CPU time 484.56 seconds
Started Mar 24 02:05:43 PM PDT 24
Finished Mar 24 02:13:48 PM PDT 24
Peak memory 259768 kb
Host smart-75a6909c-7143-4cca-be90-16690549ea0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54009422 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_error.54009422 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_error/latest

Test location /workspace/coverage/default/34.kmac_key_error.2904784906
Short name T982
Test name
Test status
Simulation time 2473207516 ps
CPU time 4.98 seconds
Started Mar 24 02:05:41 PM PDT 24
Finished Mar 24 02:05:47 PM PDT 24
Peak memory 218516 kb
Host smart-027b38be-5735-4209-8ea9-498abfcbdeae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904784906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_key_error.2904784906 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_key_error/latest

Test location /workspace/coverage/default/34.kmac_long_msg_and_output.691022140
Short name T1018
Test name
Test status
Simulation time 110942419055 ps
CPU time 1678.99 seconds
Started Mar 24 02:05:32 PM PDT 24
Finished Mar 24 02:33:32 PM PDT 24
Peak memory 347488 kb
Host smart-aac301c0-3903-48c5-bf54-3f0c71495222
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691022140 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_long_msg_an
d_output.691022140 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/34.kmac_sideload.758097062
Short name T885
Test name
Test status
Simulation time 107215675835 ps
CPU time 518.12 seconds
Started Mar 24 02:05:33 PM PDT 24
Finished Mar 24 02:14:11 PM PDT 24
Peak memory 253804 kb
Host smart-ac0572ff-dff4-4da7-bf63-8445e534ecae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758097062 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload.758097062 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_sideload/latest

Test location /workspace/coverage/default/34.kmac_smoke.2693938793
Short name T305
Test name
Test status
Simulation time 16847778713 ps
CPU time 65.07 seconds
Started Mar 24 02:05:33 PM PDT 24
Finished Mar 24 02:06:38 PM PDT 24
Peak memory 226764 kb
Host smart-eea8c0b6-7a55-4202-a1aa-99b60fbe7a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693938793 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_smoke.2693938793 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_smoke/latest

Test location /workspace/coverage/default/34.kmac_stress_all.1653609685
Short name T574
Test name
Test status
Simulation time 6893410036 ps
CPU time 635.61 seconds
Started Mar 24 02:05:41 PM PDT 24
Finished Mar 24 02:16:17 PM PDT 24
Peak memory 299468 kb
Host smart-e71fdc99-2423-4740-8623-d703059d34a1
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1653609685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all.1653609685 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all/latest

Test location /workspace/coverage/default/34.kmac_stress_all_with_rand_reset.876345766
Short name T901
Test name
Test status
Simulation time 26044499529 ps
CPU time 180.82 seconds
Started Mar 24 02:05:41 PM PDT 24
Finished Mar 24 02:08:42 PM PDT 24
Peak memory 259280 kb
Host smart-a8a1a977-923c-4697-a552-10b8760e7eb0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=876345766 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_stress_all_with_rand_reset.876345766 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac.1164131227
Short name T323
Test name
Test status
Simulation time 411394093 ps
CPU time 7.6 seconds
Started Mar 24 02:05:37 PM PDT 24
Finished Mar 24 02:05:46 PM PDT 24
Peak memory 218624 kb
Host smart-7f541660-18fd-4968-a2c6-8207c18738a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164131227 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 34.kmac_test_vectors_kmac.1164131227 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_kmac_xof.1023411582
Short name T1076
Test name
Test status
Simulation time 722949564 ps
CPU time 6.05 seconds
Started Mar 24 02:05:40 PM PDT 24
Finished Mar 24 02:05:46 PM PDT 24
Peak memory 218664 kb
Host smart-8248b99b-32fb-437d-b6b4-561d095cc187
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023411582 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 34.kmac_test_vectors_kmac_xof.1023411582 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_224.1367999685
Short name T711
Test name
Test status
Simulation time 403865028317 ps
CPU time 2603.21 seconds
Started Mar 24 02:05:34 PM PDT 24
Finished Mar 24 02:48:57 PM PDT 24
Peak memory 396996 kb
Host smart-7b027079-c05e-4a73-9e95-239d2c01efa0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1367999685 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_224.1367999685 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_256.1929459904
Short name T525
Test name
Test status
Simulation time 134443609516 ps
CPU time 2265.44 seconds
Started Mar 24 02:05:34 PM PDT 24
Finished Mar 24 02:43:21 PM PDT 24
Peak memory 396076 kb
Host smart-f9431501-edf1-4f49-99e9-247a81029cdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1929459904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_256.1929459904 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_384.2998752164
Short name T208
Test name
Test status
Simulation time 55751309513 ps
CPU time 1688.91 seconds
Started Mar 24 02:05:33 PM PDT 24
Finished Mar 24 02:33:42 PM PDT 24
Peak memory 340184 kb
Host smart-d4f2a5ed-e3fb-49da-90f0-43454a5f9aa5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2998752164 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_384.2998752164 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_sha3_512.1118550277
Short name T576
Test name
Test status
Simulation time 179436491578 ps
CPU time 1225.72 seconds
Started Mar 24 02:05:37 PM PDT 24
Finished Mar 24 02:26:04 PM PDT 24
Peak memory 301440 kb
Host smart-0ba20fb4-1218-4487-85cc-7e0fe30371ab
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1118550277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_sha3_512.1118550277 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_128.1203137141
Short name T806
Test name
Test status
Simulation time 196678118467 ps
CPU time 6364.07 seconds
Started Mar 24 02:05:38 PM PDT 24
Finished Mar 24 03:51:43 PM PDT 24
Peak memory 671920 kb
Host smart-5c29c4e1-94a3-4a92-8942-426c74f495d3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1203137141 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_128.1203137141 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/34.kmac_test_vectors_shake_256.3735481289
Short name T608
Test name
Test status
Simulation time 54471918745 ps
CPU time 4720.36 seconds
Started Mar 24 02:05:37 PM PDT 24
Finished Mar 24 03:24:19 PM PDT 24
Peak memory 577084 kb
Host smart-e32a3f73-2591-4955-ad3c-12422b9d104c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3735481289 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_test_vectors_shake_256.3735481289 +enable_masking=1 +sw_key_masked=0
Directory /workspace/34.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/35.kmac_alert_test.3383822429
Short name T406
Test name
Test status
Simulation time 30523010 ps
CPU time 0.74 seconds
Started Mar 24 02:06:15 PM PDT 24
Finished Mar 24 02:06:16 PM PDT 24
Peak memory 218472 kb
Host smart-3126a4ca-645d-4c5f-acfc-f640bad98795
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383822429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_alert_test.3383822429 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_alert_test/latest

Test location /workspace/coverage/default/35.kmac_app.1945959735
Short name T990
Test name
Test status
Simulation time 3775538480 ps
CPU time 265.3 seconds
Started Mar 24 02:06:05 PM PDT 24
Finished Mar 24 02:10:31 PM PDT 24
Peak memory 244940 kb
Host smart-a52166a4-b4d8-4acf-94a2-b401d874d18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945959735 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_app.1945959735 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_app/latest

Test location /workspace/coverage/default/35.kmac_burst_write.2683022041
Short name T547
Test name
Test status
Simulation time 87278964869 ps
CPU time 711.88 seconds
Started Mar 24 02:05:51 PM PDT 24
Finished Mar 24 02:17:43 PM PDT 24
Peak memory 235116 kb
Host smart-b196dca5-3c46-4e00-9b96-643c697a9b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2683022041 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_burst_write.2683022041 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_burst_write/latest

Test location /workspace/coverage/default/35.kmac_entropy_refresh.1016284083
Short name T804
Test name
Test status
Simulation time 139273313660 ps
CPU time 405.12 seconds
Started Mar 24 02:06:06 PM PDT 24
Finished Mar 24 02:12:51 PM PDT 24
Peak memory 250464 kb
Host smart-05fc64d9-d757-44b6-9b2a-c8f262a0a437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016284083 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_entropy_refresh.1016284083 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/35.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/35.kmac_error.197187057
Short name T968
Test name
Test status
Simulation time 12291135430 ps
CPU time 324.79 seconds
Started Mar 24 02:06:04 PM PDT 24
Finished Mar 24 02:11:29 PM PDT 24
Peak memory 259528 kb
Host smart-1552539e-71a5-4c65-8954-e6882109c890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197187057 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_error.197187057 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_error/latest

Test location /workspace/coverage/default/35.kmac_key_error.1966206270
Short name T906
Test name
Test status
Simulation time 1527444700 ps
CPU time 5.42 seconds
Started Mar 24 02:06:10 PM PDT 24
Finished Mar 24 02:06:16 PM PDT 24
Peak memory 218512 kb
Host smart-4c748ebf-8aa7-4a8a-a3cc-de1cf28c4881
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966206270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_key_error.1966206270 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_key_error/latest

Test location /workspace/coverage/default/35.kmac_lc_escalation.365055954
Short name T62
Test name
Test status
Simulation time 284990535 ps
CPU time 1.41 seconds
Started Mar 24 02:06:12 PM PDT 24
Finished Mar 24 02:06:13 PM PDT 24
Peak memory 226672 kb
Host smart-5553cd52-fe12-4548-8ac8-9fe6b0a6eef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365055954 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.365055954 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/35.kmac_lc_escalation/latest

Test location /workspace/coverage/default/35.kmac_long_msg_and_output.3080151541
Short name T681
Test name
Test status
Simulation time 173494225387 ps
CPU time 1197.56 seconds
Started Mar 24 02:05:48 PM PDT 24
Finished Mar 24 02:25:45 PM PDT 24
Peak memory 309012 kb
Host smart-957917ef-d543-41c3-bf43-ff343c84435a
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080151541 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_long_msg_a
nd_output.3080151541 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/35.kmac_sideload.1955348323
Short name T831
Test name
Test status
Simulation time 35741666906 ps
CPU time 483.73 seconds
Started Mar 24 02:05:52 PM PDT 24
Finished Mar 24 02:13:56 PM PDT 24
Peak memory 252540 kb
Host smart-47db2237-68ef-4108-9863-6eb8746fd8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955348323 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload.1955348323 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_sideload/latest

Test location /workspace/coverage/default/35.kmac_smoke.3907172861
Short name T653
Test name
Test status
Simulation time 5199471335 ps
CPU time 79.21 seconds
Started Mar 24 02:05:41 PM PDT 24
Finished Mar 24 02:07:00 PM PDT 24
Peak memory 226732 kb
Host smart-eec4d38a-9427-4692-bac4-8b64824f1243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907172861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_smoke.3907172861 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_smoke/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac.3177205698
Short name T342
Test name
Test status
Simulation time 203443828 ps
CPU time 6.14 seconds
Started Mar 24 02:06:00 PM PDT 24
Finished Mar 24 02:06:07 PM PDT 24
Peak memory 218652 kb
Host smart-e81ae7e2-a85c-40e8-8fb2-ebcb204df993
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177205698 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 35.kmac_test_vectors_kmac.3177205698 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_kmac_xof.2822237216
Short name T1080
Test name
Test status
Simulation time 443291400 ps
CPU time 6.66 seconds
Started Mar 24 02:06:04 PM PDT 24
Finished Mar 24 02:06:11 PM PDT 24
Peak memory 226564 kb
Host smart-ca37b88e-d1b3-443a-91ec-6adc3d30f0bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822237216 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 35.kmac_test_vectors_kmac_xof.2822237216 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_224.8474926
Short name T459
Test name
Test status
Simulation time 92467718835 ps
CPU time 1831.23 seconds
Started Mar 24 02:05:51 PM PDT 24
Finished Mar 24 02:36:22 PM PDT 24
Peak memory 394452 kb
Host smart-46037666-92e7-465c-8d9c-a3b8988cc872
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=8474926 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_224.8474926 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_256.561542477
Short name T184
Test name
Test status
Simulation time 69776913980 ps
CPU time 1938.51 seconds
Started Mar 24 02:05:51 PM PDT 24
Finished Mar 24 02:38:10 PM PDT 24
Peak memory 377892 kb
Host smart-631da672-915c-43cf-b928-73c405d04162
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=561542477 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_256.561542477 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_384.1886161408
Short name T824
Test name
Test status
Simulation time 16515173926 ps
CPU time 1656.36 seconds
Started Mar 24 02:05:52 PM PDT 24
Finished Mar 24 02:33:29 PM PDT 24
Peak memory 343316 kb
Host smart-a7c29f38-e2d1-47f4-bbd2-ffa33984c475
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1886161408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_384.1886161408 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_sha3_512.1135429264
Short name T584
Test name
Test status
Simulation time 124238462531 ps
CPU time 1332.62 seconds
Started Mar 24 02:05:51 PM PDT 24
Finished Mar 24 02:28:04 PM PDT 24
Peak memory 300024 kb
Host smart-3ab0c047-9ec5-45c9-bd71-ab0ce47335c3
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1135429264 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_sha3_512.1135429264 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_128.184032363
Short name T621
Test name
Test status
Simulation time 244705488163 ps
CPU time 5159.21 seconds
Started Mar 24 02:05:53 PM PDT 24
Finished Mar 24 03:31:53 PM PDT 24
Peak memory 656360 kb
Host smart-1483f58b-abe9-4a47-878c-9101014736c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=184032363 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_128.184032363 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/35.kmac_test_vectors_shake_256.1167689855
Short name T826
Test name
Test status
Simulation time 918810187675 ps
CPU time 4494.43 seconds
Started Mar 24 02:05:58 PM PDT 24
Finished Mar 24 03:20:53 PM PDT 24
Peak memory 568248 kb
Host smart-953c644f-8879-4eee-b95b-17d0e6c1ae07
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1167689855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_test_vectors_shake_256.1167689855 +enable_masking=1 +sw_key_masked=0
Directory /workspace/35.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/36.kmac_alert_test.3579925136
Short name T332
Test name
Test status
Simulation time 27704999 ps
CPU time 0.81 seconds
Started Mar 24 02:06:36 PM PDT 24
Finished Mar 24 02:06:37 PM PDT 24
Peak memory 218432 kb
Host smart-98daca46-8902-4817-bc9a-4ace0699b35b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579925136 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_alert_test.3579925136 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_alert_test/latest

Test location /workspace/coverage/default/36.kmac_app.4008474618
Short name T1002
Test name
Test status
Simulation time 17612991773 ps
CPU time 295.54 seconds
Started Mar 24 02:06:25 PM PDT 24
Finished Mar 24 02:11:20 PM PDT 24
Peak memory 245852 kb
Host smart-7d899d43-3650-4394-bfc3-abbc1d03a6e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008474618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_app.4008474618 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_app/latest

Test location /workspace/coverage/default/36.kmac_burst_write.3588072392
Short name T1052
Test name
Test status
Simulation time 14127375761 ps
CPU time 1535.25 seconds
Started Mar 24 02:06:20 PM PDT 24
Finished Mar 24 02:31:56 PM PDT 24
Peak memory 243160 kb
Host smart-891ca24d-6337-4622-842d-96336b174a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588072392 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_burst_write.3588072392 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_burst_write/latest

Test location /workspace/coverage/default/36.kmac_error.2177679857
Short name T658
Test name
Test status
Simulation time 173225052838 ps
CPU time 353.42 seconds
Started Mar 24 02:06:32 PM PDT 24
Finished Mar 24 02:12:25 PM PDT 24
Peak memory 259516 kb
Host smart-b94114c9-16f5-44e2-ad3b-343bb257ae49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177679857 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_error.2177679857 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_error/latest

Test location /workspace/coverage/default/36.kmac_key_error.3259497970
Short name T898
Test name
Test status
Simulation time 1005028844 ps
CPU time 2.31 seconds
Started Mar 24 02:06:32 PM PDT 24
Finished Mar 24 02:06:34 PM PDT 24
Peak memory 218604 kb
Host smart-15a6bd36-2839-444a-abc3-f33534657bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259497970 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_key_error.3259497970 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_key_error/latest

Test location /workspace/coverage/default/36.kmac_lc_escalation.3537862898
Short name T638
Test name
Test status
Simulation time 1720698691 ps
CPU time 10.61 seconds
Started Mar 24 02:06:37 PM PDT 24
Finished Mar 24 02:06:48 PM PDT 24
Peak memory 234916 kb
Host smart-c87be669-67cc-46a3-a181-3c5658d539fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537862898 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.3537862898 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/36.kmac_lc_escalation/latest

Test location /workspace/coverage/default/36.kmac_long_msg_and_output.4050321204
Short name T976
Test name
Test status
Simulation time 2191958198 ps
CPU time 85.69 seconds
Started Mar 24 02:06:16 PM PDT 24
Finished Mar 24 02:07:42 PM PDT 24
Peak memory 239632 kb
Host smart-3c86d554-1ece-43fd-8cd5-739100e0ea25
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050321204 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_long_msg_a
nd_output.4050321204 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/36.kmac_sideload.2658203925
Short name T470
Test name
Test status
Simulation time 56863492919 ps
CPU time 313.88 seconds
Started Mar 24 02:06:16 PM PDT 24
Finished Mar 24 02:11:30 PM PDT 24
Peak memory 243748 kb
Host smart-2eccf348-46d7-4de5-85fc-9d1eb487f770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658203925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload.2658203925 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_sideload/latest

Test location /workspace/coverage/default/36.kmac_smoke.253033653
Short name T1039
Test name
Test status
Simulation time 7475945025 ps
CPU time 57.31 seconds
Started Mar 24 02:06:14 PM PDT 24
Finished Mar 24 02:07:13 PM PDT 24
Peak memory 226720 kb
Host smart-9c867e64-ca38-4010-b1bb-9cb46fcd4edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253033653 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_smoke.253033653 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_smoke/latest

Test location /workspace/coverage/default/36.kmac_stress_all_with_rand_reset.1975442995
Short name T741
Test name
Test status
Simulation time 13801924197 ps
CPU time 828.89 seconds
Started Mar 24 02:06:37 PM PDT 24
Finished Mar 24 02:20:26 PM PDT 24
Peak memory 301540 kb
Host smart-96efc6aa-e418-4927-9f11-03a024cb0109
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1975442995 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_stress_all_with_rand_reset.1975442995 +e
nable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac.3306408495
Short name T222
Test name
Test status
Simulation time 960949677 ps
CPU time 6.97 seconds
Started Mar 24 02:06:26 PM PDT 24
Finished Mar 24 02:06:33 PM PDT 24
Peak memory 226764 kb
Host smart-6e86a795-d428-4ce9-8268-231d7b334076
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306408495 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 36.kmac_test_vectors_kmac.3306408495 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_kmac_xof.1043636654
Short name T252
Test name
Test status
Simulation time 1035791402 ps
CPU time 6.22 seconds
Started Mar 24 02:06:25 PM PDT 24
Finished Mar 24 02:06:31 PM PDT 24
Peak memory 226720 kb
Host smart-133bd7b1-19a1-4b6b-b5bc-98f3de28f396
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043636654 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 36.kmac_test_vectors_kmac_xof.1043636654 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_224.3042503128
Short name T180
Test name
Test status
Simulation time 263139428241 ps
CPU time 2295.55 seconds
Started Mar 24 02:06:21 PM PDT 24
Finished Mar 24 02:44:37 PM PDT 24
Peak memory 399392 kb
Host smart-39efc0e9-e4c4-4a42-af02-394dde8ee76b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3042503128 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_224.3042503128 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_256.4050711671
Short name T1067
Test name
Test status
Simulation time 21628148439 ps
CPU time 1983.01 seconds
Started Mar 24 02:06:20 PM PDT 24
Finished Mar 24 02:39:23 PM PDT 24
Peak memory 387304 kb
Host smart-9191828d-5bc3-440f-ba38-b59d58fdb094
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4050711671 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_256.4050711671 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_384.1268983734
Short name T558
Test name
Test status
Simulation time 41485820757 ps
CPU time 1607.79 seconds
Started Mar 24 02:06:19 PM PDT 24
Finished Mar 24 02:33:07 PM PDT 24
Peak memory 338196 kb
Host smart-418852f6-f6bf-47f1-9aa1-4cba05e5b4a7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1268983734 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_384.1268983734 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_sha3_512.168704283
Short name T1082
Test name
Test status
Simulation time 11089605104 ps
CPU time 1194.37 seconds
Started Mar 24 02:06:26 PM PDT 24
Finished Mar 24 02:26:20 PM PDT 24
Peak memory 297660 kb
Host smart-7a043e00-135d-4ecf-bcac-2385bca77369
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=168704283 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_sha3_512.168704283 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_128.4124496763
Short name T743
Test name
Test status
Simulation time 259592648807 ps
CPU time 6481.25 seconds
Started Mar 24 02:06:24 PM PDT 24
Finished Mar 24 03:54:27 PM PDT 24
Peak memory 654836 kb
Host smart-c94e5bfd-c5cf-4db2-8093-7ce08e5981e8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4124496763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_128.4124496763 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/36.kmac_test_vectors_shake_256.1687281676
Short name T356
Test name
Test status
Simulation time 624380076804 ps
CPU time 5058.51 seconds
Started Mar 24 02:06:24 PM PDT 24
Finished Mar 24 03:30:43 PM PDT 24
Peak memory 563304 kb
Host smart-873bb2b7-b740-453b-9bb5-93280978441e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1687281676 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_test_vectors_shake_256.1687281676 +enable_masking=1 +sw_key_masked=0
Directory /workspace/36.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/37.kmac_alert_test.2232800561
Short name T571
Test name
Test status
Simulation time 22985204 ps
CPU time 0.87 seconds
Started Mar 24 02:07:01 PM PDT 24
Finished Mar 24 02:07:02 PM PDT 24
Peak memory 218720 kb
Host smart-7b9da807-8d09-419d-ac75-e705648486f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232800561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_alert_test.2232800561 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_alert_test/latest

Test location /workspace/coverage/default/37.kmac_app.2602975383
Short name T617
Test name
Test status
Simulation time 11588911821 ps
CPU time 227.12 seconds
Started Mar 24 02:06:52 PM PDT 24
Finished Mar 24 02:10:39 PM PDT 24
Peak memory 243324 kb
Host smart-7724780a-e518-4e12-8e3f-4f19a84764c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602975383 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_app.2602975383 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_app/latest

Test location /workspace/coverage/default/37.kmac_burst_write.1540180071
Short name T882
Test name
Test status
Simulation time 965474363 ps
CPU time 53.82 seconds
Started Mar 24 02:06:43 PM PDT 24
Finished Mar 24 02:07:37 PM PDT 24
Peak memory 224344 kb
Host smart-1df74b0e-39db-4617-87cc-13669929ff81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540180071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_burst_write.1540180071 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_burst_write/latest

Test location /workspace/coverage/default/37.kmac_entropy_refresh.3682805329
Short name T362
Test name
Test status
Simulation time 47210717364 ps
CPU time 310.91 seconds
Started Mar 24 02:06:52 PM PDT 24
Finished Mar 24 02:12:03 PM PDT 24
Peak memory 246976 kb
Host smart-e5285e1c-c716-4edb-b508-5a886783fa4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682805329 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_entropy_refresh.3682805329 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/37.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/37.kmac_error.3621252917
Short name T211
Test name
Test status
Simulation time 2793984828 ps
CPU time 235.11 seconds
Started Mar 24 02:06:52 PM PDT 24
Finished Mar 24 02:10:47 PM PDT 24
Peak memory 251604 kb
Host smart-a5676d33-ec1d-4fda-a235-cb0e268a8368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621252917 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_error.3621252917 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_error/latest

Test location /workspace/coverage/default/37.kmac_key_error.1566770094
Short name T800
Test name
Test status
Simulation time 1317974835 ps
CPU time 4.13 seconds
Started Mar 24 02:06:56 PM PDT 24
Finished Mar 24 02:07:00 PM PDT 24
Peak memory 218520 kb
Host smart-7f005743-f9bf-4994-9b9f-69fd9edaeb76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566770094 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_key_error.1566770094 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_key_error/latest

Test location /workspace/coverage/default/37.kmac_lc_escalation.3788005132
Short name T73
Test name
Test status
Simulation time 1620791596 ps
CPU time 23.49 seconds
Started Mar 24 02:06:58 PM PDT 24
Finished Mar 24 02:07:21 PM PDT 24
Peak memory 233108 kb
Host smart-5d5c1cdb-1c1e-46c1-ab6e-3c73e447fb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788005132 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.3788005132 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/37.kmac_lc_escalation/latest

Test location /workspace/coverage/default/37.kmac_long_msg_and_output.2613674005
Short name T625
Test name
Test status
Simulation time 17396100838 ps
CPU time 441.55 seconds
Started Mar 24 02:06:37 PM PDT 24
Finished Mar 24 02:13:58 PM PDT 24
Peak memory 263632 kb
Host smart-08f5d755-3343-49a3-9c1d-7c0dc8d91cbe
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613674005 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_long_msg_a
nd_output.2613674005 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/37.kmac_sideload.2380705079
Short name T763
Test name
Test status
Simulation time 79162678499 ps
CPU time 531.99 seconds
Started Mar 24 02:06:42 PM PDT 24
Finished Mar 24 02:15:34 PM PDT 24
Peak memory 251044 kb
Host smart-34f7b01d-c31c-4207-9d21-39109aa914c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380705079 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload.2380705079 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_sideload/latest

Test location /workspace/coverage/default/37.kmac_smoke.1842412168
Short name T175
Test name
Test status
Simulation time 16881662543 ps
CPU time 83 seconds
Started Mar 24 02:06:37 PM PDT 24
Finished Mar 24 02:08:00 PM PDT 24
Peak memory 226772 kb
Host smart-117b1632-110a-4b2a-bfe7-b606c7d47175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842412168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_smoke.1842412168 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_smoke/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac.673068775
Short name T456
Test name
Test status
Simulation time 388742857 ps
CPU time 5.62 seconds
Started Mar 24 02:06:51 PM PDT 24
Finished Mar 24 02:06:56 PM PDT 24
Peak memory 226716 kb
Host smart-8d2e7764-9956-4291-985d-d56ef5a5a74f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673068775 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 37.kmac_test_vectors_kmac.673068775 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_kmac_xof.1538357039
Short name T569
Test name
Test status
Simulation time 948860723 ps
CPU time 6.35 seconds
Started Mar 24 02:06:51 PM PDT 24
Finished Mar 24 02:06:57 PM PDT 24
Peak memory 218500 kb
Host smart-b9122952-17e0-425f-b301-0cd8a7553827
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538357039 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 37.kmac_test_vectors_kmac_xof.1538357039 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_224.3000126335
Short name T291
Test name
Test status
Simulation time 101698148754 ps
CPU time 2413.5 seconds
Started Mar 24 02:06:42 PM PDT 24
Finished Mar 24 02:46:55 PM PDT 24
Peak memory 392752 kb
Host smart-e603ec7a-fe1c-4a21-bd98-d41befd8f986
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3000126335 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_224.3000126335 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_256.4073510019
Short name T902
Test name
Test status
Simulation time 99148276605 ps
CPU time 1929.63 seconds
Started Mar 24 02:06:46 PM PDT 24
Finished Mar 24 02:38:56 PM PDT 24
Peak memory 380788 kb
Host smart-30a0ead6-167b-4278-bb45-2777d2b5a50a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4073510019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_256.4073510019 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_384.3820162562
Short name T338
Test name
Test status
Simulation time 529944709233 ps
CPU time 1800.78 seconds
Started Mar 24 02:06:46 PM PDT 24
Finished Mar 24 02:36:48 PM PDT 24
Peak memory 335324 kb
Host smart-fc3491d8-0275-4365-ad28-11f548e74e89
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3820162562 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_384.3820162562 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_sha3_512.1510344501
Short name T399
Test name
Test status
Simulation time 11712721593 ps
CPU time 1144.08 seconds
Started Mar 24 02:06:47 PM PDT 24
Finished Mar 24 02:25:51 PM PDT 24
Peak memory 300880 kb
Host smart-24cbb998-d2a7-4be5-a218-616a41c97e19
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1510344501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_sha3_512.1510344501 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_128.496127377
Short name T721
Test name
Test status
Simulation time 884188508512 ps
CPU time 6425.04 seconds
Started Mar 24 02:06:48 PM PDT 24
Finished Mar 24 03:53:54 PM PDT 24
Peak memory 658116 kb
Host smart-916ecda8-c915-4311-8da9-e175509232e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=496127377 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_128.496127377 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/37.kmac_test_vectors_shake_256.3775369278
Short name T592
Test name
Test status
Simulation time 217500220493 ps
CPU time 4430.74 seconds
Started Mar 24 02:06:47 PM PDT 24
Finished Mar 24 03:20:38 PM PDT 24
Peak memory 561112 kb
Host smart-8f09be53-8c10-45f9-bf14-9aa752a0cd33
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3775369278 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_test_vectors_shake_256.3775369278 +enable_masking=1 +sw_key_masked=0
Directory /workspace/37.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/38.kmac_alert_test.3172953948
Short name T890
Test name
Test status
Simulation time 40587744 ps
CPU time 0.82 seconds
Started Mar 24 02:07:31 PM PDT 24
Finished Mar 24 02:07:32 PM PDT 24
Peak memory 218504 kb
Host smart-15abfbdd-c8d1-4b8a-845a-f42c4954ba35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172953948 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_alert_test.3172953948 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_alert_test/latest

Test location /workspace/coverage/default/38.kmac_app.32164627
Short name T165
Test name
Test status
Simulation time 60801631398 ps
CPU time 426.88 seconds
Started Mar 24 02:07:22 PM PDT 24
Finished Mar 24 02:14:29 PM PDT 24
Peak memory 253484 kb
Host smart-549b4662-a2f5-4eab-a816-179764a2ead5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=32164627 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_app.32164627 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_app/latest

Test location /workspace/coverage/default/38.kmac_burst_write.3043637413
Short name T719
Test name
Test status
Simulation time 53993652085 ps
CPU time 1318.45 seconds
Started Mar 24 02:07:07 PM PDT 24
Finished Mar 24 02:29:06 PM PDT 24
Peak memory 237596 kb
Host smart-79247d72-0437-460f-b189-3a0815f8de19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043637413 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_burst_write.3043637413 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_burst_write/latest

Test location /workspace/coverage/default/38.kmac_entropy_refresh.3458098107
Short name T311
Test name
Test status
Simulation time 42465386829 ps
CPU time 284.1 seconds
Started Mar 24 02:07:22 PM PDT 24
Finished Mar 24 02:12:06 PM PDT 24
Peak memory 246976 kb
Host smart-1db0aa16-566b-4a6d-9358-9045e9e4c551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458098107 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_entropy_refresh.3458098107 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/38.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/38.kmac_error.346538287
Short name T852
Test name
Test status
Simulation time 20006683242 ps
CPU time 276.92 seconds
Started Mar 24 02:07:19 PM PDT 24
Finished Mar 24 02:11:56 PM PDT 24
Peak memory 254108 kb
Host smart-9fa76b43-7570-44ec-9c05-3564a6cdc288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346538287 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_error.346538287 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_error/latest

Test location /workspace/coverage/default/38.kmac_key_error.400968981
Short name T526
Test name
Test status
Simulation time 4959824135 ps
CPU time 6.01 seconds
Started Mar 24 02:07:25 PM PDT 24
Finished Mar 24 02:07:33 PM PDT 24
Peak memory 218804 kb
Host smart-84347b08-2ed9-4e71-8456-ba9c628963b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400968981 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_key_error.400968981 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_key_error/latest

Test location /workspace/coverage/default/38.kmac_lc_escalation.297284700
Short name T846
Test name
Test status
Simulation time 40776810 ps
CPU time 1.4 seconds
Started Mar 24 02:07:26 PM PDT 24
Finished Mar 24 02:07:29 PM PDT 24
Peak memory 218620 kb
Host smart-2eee2b0f-5168-4fcc-a0a8-2d593fd9268f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297284700 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.297284700 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/38.kmac_lc_escalation/latest

Test location /workspace/coverage/default/38.kmac_long_msg_and_output.1832870032
Short name T486
Test name
Test status
Simulation time 601894836530 ps
CPU time 2522.96 seconds
Started Mar 24 02:07:07 PM PDT 24
Finished Mar 24 02:49:11 PM PDT 24
Peak memory 394548 kb
Host smart-a601f404-dedd-40de-b2ef-bb971864ae31
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832870032 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_long_msg_a
nd_output.1832870032 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/38.kmac_sideload.3402894457
Short name T444
Test name
Test status
Simulation time 3210928013 ps
CPU time 112.52 seconds
Started Mar 24 02:07:07 PM PDT 24
Finished Mar 24 02:09:00 PM PDT 24
Peak memory 236172 kb
Host smart-d6bb905e-2e84-4358-83fc-f6019f4b6f72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402894457 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload.3402894457 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_sideload/latest

Test location /workspace/coverage/default/38.kmac_smoke.127072616
Short name T1026
Test name
Test status
Simulation time 18736739800 ps
CPU time 50.05 seconds
Started Mar 24 02:07:01 PM PDT 24
Finished Mar 24 02:07:52 PM PDT 24
Peak memory 226796 kb
Host smart-80203c0c-4619-4eca-b25e-babaf5b5b104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127072616 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_smoke.127072616 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_smoke/latest

Test location /workspace/coverage/default/38.kmac_stress_all.949651394
Short name T732
Test name
Test status
Simulation time 137160057792 ps
CPU time 843.33 seconds
Started Mar 24 02:07:30 PM PDT 24
Finished Mar 24 02:21:34 PM PDT 24
Peak memory 305756 kb
Host smart-03f90b83-9f7d-45c7-b54e-3f84d6865911
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=949651394 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_stress_all.949651394 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_stress_all/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac.4153765603
Short name T867
Test name
Test status
Simulation time 497498434 ps
CPU time 6.25 seconds
Started Mar 24 02:07:20 PM PDT 24
Finished Mar 24 02:07:27 PM PDT 24
Peak memory 218676 kb
Host smart-1e9b5d22-52d4-4a83-8769-edde2f2dbcd0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153765603 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 38.kmac_test_vectors_kmac.4153765603 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_kmac_xof.1919259288
Short name T812
Test name
Test status
Simulation time 436770632 ps
CPU time 6.27 seconds
Started Mar 24 02:07:19 PM PDT 24
Finished Mar 24 02:07:26 PM PDT 24
Peak memory 218708 kb
Host smart-6c8c6487-113f-4462-a2d0-ef8e7e966c7b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919259288 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 38.kmac_test_vectors_kmac_xof.1919259288 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_224.1390593337
Short name T785
Test name
Test status
Simulation time 177473276474 ps
CPU time 2273.25 seconds
Started Mar 24 02:07:07 PM PDT 24
Finished Mar 24 02:45:01 PM PDT 24
Peak memory 399832 kb
Host smart-de9957aa-a50d-42f9-8548-d79bac30820e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1390593337 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_224.1390593337 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_256.960997151
Short name T734
Test name
Test status
Simulation time 123222358304 ps
CPU time 1986.11 seconds
Started Mar 24 02:07:10 PM PDT 24
Finished Mar 24 02:40:17 PM PDT 24
Peak memory 393380 kb
Host smart-f4d1b168-42e1-4e34-b275-b0bb681834a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=960997151 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_256.960997151 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_384.1871754792
Short name T538
Test name
Test status
Simulation time 15664104098 ps
CPU time 1621.83 seconds
Started Mar 24 02:07:13 PM PDT 24
Finished Mar 24 02:34:17 PM PDT 24
Peak memory 345472 kb
Host smart-52ed0ca8-4260-465c-8c4c-1d9e7d480c3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1871754792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_384.1871754792 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_sha3_512.4187348129
Short name T1068
Test name
Test status
Simulation time 642198585806 ps
CPU time 1428.29 seconds
Started Mar 24 02:07:13 PM PDT 24
Finished Mar 24 02:31:03 PM PDT 24
Peak memory 309296 kb
Host smart-57207abc-0c2f-47fa-ad8c-9eb9afefc575
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4187348129 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_sha3_512.4187348129 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_128.873235447
Short name T367
Test name
Test status
Simulation time 142071808291 ps
CPU time 4965.28 seconds
Started Mar 24 02:07:15 PM PDT 24
Finished Mar 24 03:30:01 PM PDT 24
Peak memory 655384 kb
Host smart-2dd6b718-b683-4ec2-952d-5d500419cca6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=873235447 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_128.873235447 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/38.kmac_test_vectors_shake_256.272440236
Short name T33
Test name
Test status
Simulation time 116405388829 ps
CPU time 4323.24 seconds
Started Mar 24 02:07:15 PM PDT 24
Finished Mar 24 03:19:19 PM PDT 24
Peak memory 574904 kb
Host smart-fd406df6-4b21-4b79-887b-538226c3e5f4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=272440236 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_test_vectors_shake_256.272440236 +enable_masking=1 +sw_key_masked=0
Directory /workspace/38.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/39.kmac_alert_test.4283838578
Short name T178
Test name
Test status
Simulation time 28123184 ps
CPU time 0.85 seconds
Started Mar 24 02:07:55 PM PDT 24
Finished Mar 24 02:07:56 PM PDT 24
Peak memory 218484 kb
Host smart-e931f423-6027-4d7d-8ee3-809b0dc2fd1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283838578 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_alert_test.4283838578 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_alert_test/latest

Test location /workspace/coverage/default/39.kmac_app.3117080191
Short name T620
Test name
Test status
Simulation time 5406765059 ps
CPU time 170.65 seconds
Started Mar 24 02:07:46 PM PDT 24
Finished Mar 24 02:10:38 PM PDT 24
Peak memory 238180 kb
Host smart-60dc6835-3246-4a19-a2f2-0f0ad1be5532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117080191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_app.3117080191 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_app/latest

Test location /workspace/coverage/default/39.kmac_burst_write.3097111564
Short name T254
Test name
Test status
Simulation time 156001501522 ps
CPU time 1559.71 seconds
Started Mar 24 02:07:29 PM PDT 24
Finished Mar 24 02:33:30 PM PDT 24
Peak memory 239692 kb
Host smart-49377f26-261d-4993-8600-beb8ee4b4eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097111564 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_burst_write.3097111564 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_burst_write/latest

Test location /workspace/coverage/default/39.kmac_entropy_refresh.1077691253
Short name T308
Test name
Test status
Simulation time 30794195467 ps
CPU time 361.99 seconds
Started Mar 24 02:07:46 PM PDT 24
Finished Mar 24 02:13:48 PM PDT 24
Peak memory 248916 kb
Host smart-ae5c1242-c668-4174-bee1-cb4dd8490d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077691253 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_entropy_refresh.1077691253 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/39.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/39.kmac_error.1712492056
Short name T56
Test name
Test status
Simulation time 37033016448 ps
CPU time 266.12 seconds
Started Mar 24 02:07:45 PM PDT 24
Finished Mar 24 02:12:11 PM PDT 24
Peak memory 259524 kb
Host smart-167ed073-ed4f-484d-b1b7-41a53fce37df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712492056 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_error.1712492056 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_error/latest

Test location /workspace/coverage/default/39.kmac_key_error.4220286702
Short name T560
Test name
Test status
Simulation time 909121180 ps
CPU time 3.07 seconds
Started Mar 24 02:07:50 PM PDT 24
Finished Mar 24 02:07:53 PM PDT 24
Peak memory 218512 kb
Host smart-3c24d53a-caa7-4929-aea4-de3caba2143f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220286702 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_key_error.4220286702 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_key_error/latest

Test location /workspace/coverage/default/39.kmac_lc_escalation.3942600180
Short name T1064
Test name
Test status
Simulation time 70196282 ps
CPU time 1.43 seconds
Started Mar 24 02:07:51 PM PDT 24
Finished Mar 24 02:07:52 PM PDT 24
Peak memory 218608 kb
Host smart-0d44c71c-22b6-4a0e-8573-b934114243df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942600180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.3942600180 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/39.kmac_lc_escalation/latest

Test location /workspace/coverage/default/39.kmac_long_msg_and_output.4050180586
Short name T100
Test name
Test status
Simulation time 131045584128 ps
CPU time 838.06 seconds
Started Mar 24 02:07:31 PM PDT 24
Finished Mar 24 02:21:29 PM PDT 24
Peak memory 287196 kb
Host smart-c2d40907-bd33-42b2-bee5-1f186a4278b2
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050180586 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_long_msg_a
nd_output.4050180586 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/39.kmac_sideload.2843081810
Short name T1032
Test name
Test status
Simulation time 3038414966 ps
CPU time 302.45 seconds
Started Mar 24 02:07:29 PM PDT 24
Finished Mar 24 02:12:33 PM PDT 24
Peak memory 245408 kb
Host smart-307b0cd5-7a84-48d3-9100-ccb9d7d4b80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843081810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload.2843081810 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_sideload/latest

Test location /workspace/coverage/default/39.kmac_smoke.3026309787
Short name T1037
Test name
Test status
Simulation time 4559832610 ps
CPU time 56.22 seconds
Started Mar 24 02:07:30 PM PDT 24
Finished Mar 24 02:08:27 PM PDT 24
Peak memory 226764 kb
Host smart-58784fe8-613e-4a54-be62-690e847977eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026309787 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_smoke.3026309787 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_smoke/latest

Test location /workspace/coverage/default/39.kmac_stress_all.3638133170
Short name T279
Test name
Test status
Simulation time 18911875621 ps
CPU time 517.38 seconds
Started Mar 24 02:07:49 PM PDT 24
Finished Mar 24 02:16:27 PM PDT 24
Peak memory 275864 kb
Host smart-bb1b8e1c-a9a2-42a3-bf52-50e78633b0cd
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3638133170 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_stress_all.3638133170 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_stress_all/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac.599581352
Short name T755
Test name
Test status
Simulation time 230517770 ps
CPU time 7.08 seconds
Started Mar 24 02:07:38 PM PDT 24
Finished Mar 24 02:07:45 PM PDT 24
Peak memory 226752 kb
Host smart-1316c8d6-43db-44aa-84d1-73d6f366ebb8
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599581352 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 39.kmac_test_vectors_kmac.599581352 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_kmac_xof.680647333
Short name T390
Test name
Test status
Simulation time 484233924 ps
CPU time 6.66 seconds
Started Mar 24 02:07:45 PM PDT 24
Finished Mar 24 02:07:52 PM PDT 24
Peak memory 226920 kb
Host smart-f26fdc1a-cd66-4524-ab92-5f4dfdd6608b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=680647333 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 39.kmac_test_vectors_kmac_xof.680647333 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_224.2616542429
Short name T589
Test name
Test status
Simulation time 596609204537 ps
CPU time 2588.16 seconds
Started Mar 24 02:07:34 PM PDT 24
Finished Mar 24 02:50:43 PM PDT 24
Peak memory 391408 kb
Host smart-09d1ca47-ab32-40e2-b526-55b002e11137
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2616542429 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_224.2616542429 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_256.4012321297
Short name T865
Test name
Test status
Simulation time 21954665967 ps
CPU time 1991.18 seconds
Started Mar 24 02:07:34 PM PDT 24
Finished Mar 24 02:40:46 PM PDT 24
Peak memory 388952 kb
Host smart-609b941c-78a5-446f-82d3-992229a515b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4012321297 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_256.4012321297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_384.3562715126
Short name T210
Test name
Test status
Simulation time 30531083464 ps
CPU time 1587.49 seconds
Started Mar 24 02:07:33 PM PDT 24
Finished Mar 24 02:34:01 PM PDT 24
Peak memory 339980 kb
Host smart-67caf2d7-d8d9-406f-9d07-fc67b9f08ce6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3562715126 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_384.3562715126 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_sha3_512.2614144182
Short name T704
Test name
Test status
Simulation time 141945416852 ps
CPU time 1389.32 seconds
Started Mar 24 02:07:41 PM PDT 24
Finished Mar 24 02:30:50 PM PDT 24
Peak memory 305400 kb
Host smart-fe80d22d-75c1-4d14-b76e-d91a20d2d6c4
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2614144182 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_sha3_512.2614144182 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_128.417901749
Short name T614
Test name
Test status
Simulation time 297200448108 ps
CPU time 6335.09 seconds
Started Mar 24 02:07:38 PM PDT 24
Finished Mar 24 03:53:14 PM PDT 24
Peak memory 653536 kb
Host smart-c724e1ac-1343-42c0-bb0a-6413a10a0063
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=417901749 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_128.417901749 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/39.kmac_test_vectors_shake_256.458107417
Short name T684
Test name
Test status
Simulation time 156836581055 ps
CPU time 5081.46 seconds
Started Mar 24 02:07:40 PM PDT 24
Finished Mar 24 03:32:23 PM PDT 24
Peak memory 575396 kb
Host smart-ac962abf-81e0-4fbf-9d3c-1ca0457678e6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=458107417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_test_vectors_shake_256.458107417 +enable_masking=1 +sw_key_masked=0
Directory /workspace/39.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/4.kmac_alert_test.3809486223
Short name T642
Test name
Test status
Simulation time 26785462 ps
CPU time 0.82 seconds
Started Mar 24 01:57:54 PM PDT 24
Finished Mar 24 01:57:55 PM PDT 24
Peak memory 218756 kb
Host smart-97f8b9b0-e425-4e76-a8d6-464ffd994283
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809486223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.3809486223 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_alert_test/latest

Test location /workspace/coverage/default/4.kmac_app.3594177944
Short name T543
Test name
Test status
Simulation time 9029432807 ps
CPU time 208.65 seconds
Started Mar 24 01:57:51 PM PDT 24
Finished Mar 24 02:01:20 PM PDT 24
Peak memory 243140 kb
Host smart-e5a84167-4ec5-4c5a-827b-61604778bde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594177944 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.3594177944 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app/latest

Test location /workspace/coverage/default/4.kmac_app_with_partial_data.1138269798
Short name T277
Test name
Test status
Simulation time 13809802640 ps
CPU time 147.49 seconds
Started Mar 24 01:57:50 PM PDT 24
Finished Mar 24 02:00:18 PM PDT 24
Peak memory 236056 kb
Host smart-b587d471-829e-48c3-9ff3-06cc32b8d344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138269798 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.1138269798 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/4.kmac_burst_write.606401525
Short name T398
Test name
Test status
Simulation time 18853522223 ps
CPU time 1709.8 seconds
Started Mar 24 01:57:51 PM PDT 24
Finished Mar 24 02:26:21 PM PDT 24
Peak memory 237968 kb
Host smart-af043dc9-18d5-40f8-869d-f78b83efc184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606401525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.606401525 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_burst_write/latest

Test location /workspace/coverage/default/4.kmac_edn_timeout_error.3698059316
Short name T15
Test name
Test status
Simulation time 18545159 ps
CPU time 0.93 seconds
Started Mar 24 01:58:00 PM PDT 24
Finished Mar 24 01:58:01 PM PDT 24
Peak memory 218432 kb
Host smart-ee934b18-6617-4ea5-abfa-78840d20060a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3698059316 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3698059316 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_mode_error.685156712
Short name T71
Test name
Test status
Simulation time 15632787 ps
CPU time 0.83 seconds
Started Mar 24 01:57:54 PM PDT 24
Finished Mar 24 01:57:55 PM PDT 24
Peak memory 220524 kb
Host smart-70e7b320-0b3a-44d6-bb13-a0a07bc003ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=685156712 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.685156712 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_ready_error.1108858
Short name T52
Test name
Test status
Simulation time 6158364469 ps
CPU time 57.58 seconds
Started Mar 24 01:58:01 PM PDT 24
Finished Mar 24 01:58:59 PM PDT 24
Peak memory 226740 kb
Host smart-43492a09-c194-440a-9a87-2b573b5a73cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.1108858 +enable_masking=1
+sw_key_masked=0
Directory /workspace/4.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/4.kmac_entropy_refresh.755113684
Short name T955
Test name
Test status
Simulation time 17246332957 ps
CPU time 167.31 seconds
Started Mar 24 01:57:52 PM PDT 24
Finished Mar 24 02:00:40 PM PDT 24
Peak memory 238060 kb
Host smart-779a94c0-144c-4edd-b607-afeda5cd75b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755113684 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.755113684 +enable_masking=1 +sw_
key_masked=0
Directory /workspace/4.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/4.kmac_error.1186198492
Short name T985
Test name
Test status
Simulation time 1185958251 ps
CPU time 10.14 seconds
Started Mar 24 01:57:50 PM PDT 24
Finished Mar 24 01:58:00 PM PDT 24
Peak memory 226696 kb
Host smart-0dadf71c-c1a0-4b47-92d2-36335235eb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186198492 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.1186198492 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_error/latest

Test location /workspace/coverage/default/4.kmac_key_error.4045950019
Short name T992
Test name
Test status
Simulation time 3635767760 ps
CPU time 5.4 seconds
Started Mar 24 01:57:49 PM PDT 24
Finished Mar 24 01:57:55 PM PDT 24
Peak memory 218556 kb
Host smart-49e935ae-e324-4abb-8ddc-8f01e1145135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045950019 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.4045950019 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_key_error/latest

Test location /workspace/coverage/default/4.kmac_lc_escalation.4113077177
Short name T72
Test name
Test status
Simulation time 60879550 ps
CPU time 1.47 seconds
Started Mar 24 01:57:55 PM PDT 24
Finished Mar 24 01:57:57 PM PDT 24
Peak memory 218852 kb
Host smart-54d4d9ff-df1a-4157-ae74-42c82d683495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113077177 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.4113077177 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/4.kmac_lc_escalation/latest

Test location /workspace/coverage/default/4.kmac_long_msg_and_output.1881420360
Short name T675
Test name
Test status
Simulation time 53858071443 ps
CPU time 2101.89 seconds
Started Mar 24 01:57:50 PM PDT 24
Finished Mar 24 02:32:52 PM PDT 24
Peak memory 381052 kb
Host smart-4b4c4ee0-1887-40b6-bf90-5a1796b59ed7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881420360 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_an
d_output.1881420360 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/4.kmac_mubi.3592726111
Short name T834
Test name
Test status
Simulation time 20513305242 ps
CPU time 155.82 seconds
Started Mar 24 01:57:51 PM PDT 24
Finished Mar 24 02:00:27 PM PDT 24
Peak memory 237728 kb
Host smart-7b61a989-0459-4e80-b199-98331ccf260f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592726111 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.3592726111 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_mubi/latest

Test location /workspace/coverage/default/4.kmac_sec_cm.416394632
Short name T30
Test name
Test status
Simulation time 2556296778 ps
CPU time 41.37 seconds
Started Mar 24 01:58:00 PM PDT 24
Finished Mar 24 01:58:41 PM PDT 24
Peak memory 256752 kb
Host smart-a384393d-6fc7-4438-ba8f-cf61fdcd6f34
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416394632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.416394632 +enable_masking
=1 +sw_key_masked=0
Directory /workspace/4.kmac_sec_cm/latest

Test location /workspace/coverage/default/4.kmac_sideload.2389545805
Short name T922
Test name
Test status
Simulation time 1444974344 ps
CPU time 46.97 seconds
Started Mar 24 01:57:50 PM PDT 24
Finished Mar 24 01:58:38 PM PDT 24
Peak memory 225752 kb
Host smart-16c53861-6138-43d8-a26d-ba92dabe8273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389545805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.2389545805 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_sideload/latest

Test location /workspace/coverage/default/4.kmac_smoke.1683035708
Short name T913
Test name
Test status
Simulation time 9870773406 ps
CPU time 84.88 seconds
Started Mar 24 01:57:52 PM PDT 24
Finished Mar 24 01:59:17 PM PDT 24
Peak memory 226744 kb
Host smart-afd157cd-8ca9-4cc1-a953-7b9037c451ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683035708 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.1683035708 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_smoke/latest

Test location /workspace/coverage/default/4.kmac_stress_all.1944386825
Short name T534
Test name
Test status
Simulation time 171942018349 ps
CPU time 1045.51 seconds
Started Mar 24 01:57:55 PM PDT 24
Finished Mar 24 02:15:20 PM PDT 24
Peak memory 318416 kb
Host smart-6306b05d-f874-43fe-9f2f-de8b68ecfdc5
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1944386825 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all.1944386825 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all/latest

Test location /workspace/coverage/default/4.kmac_stress_all_with_rand_reset.4080901677
Short name T121
Test name
Test status
Simulation time 202103140016 ps
CPU time 1354.62 seconds
Started Mar 24 01:57:56 PM PDT 24
Finished Mar 24 02:20:30 PM PDT 24
Peak memory 338516 kb
Host smart-eba93440-0d1d-4202-a87c-f0456d0a96bf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4080901677 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all_with_rand_reset.4080901677 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac.442585696
Short name T740
Test name
Test status
Simulation time 1157437463 ps
CPU time 6.74 seconds
Started Mar 24 01:57:51 PM PDT 24
Finished Mar 24 01:57:58 PM PDT 24
Peak memory 218572 kb
Host smart-5d5a5d3c-fd11-4130-8209-0ea76eb41bdf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442585696 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 4.kmac_test_vectors_kmac.442585696 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_kmac_xof.3549180513
Short name T396
Test name
Test status
Simulation time 449436688 ps
CPU time 5.94 seconds
Started Mar 24 01:57:50 PM PDT 24
Finished Mar 24 01:57:56 PM PDT 24
Peak memory 226744 kb
Host smart-bf5d15e8-c4e8-4468-b343-2a68937e9ffe
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549180513 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 4.kmac_test_vectors_kmac_xof.3549180513 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_224.2183473513
Short name T1079
Test name
Test status
Simulation time 68931661238 ps
CPU time 2132 seconds
Started Mar 24 01:57:52 PM PDT 24
Finished Mar 24 02:33:25 PM PDT 24
Peak memory 406568 kb
Host smart-b90c6c8d-922b-4c8b-9df5-9030fb1f62e2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2183473513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.2183473513 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_256.522388417
Short name T595
Test name
Test status
Simulation time 129718382630 ps
CPU time 2057.86 seconds
Started Mar 24 01:57:50 PM PDT 24
Finished Mar 24 02:32:08 PM PDT 24
Peak memory 388296 kb
Host smart-4ca8da0a-1461-4f45-bdda-baecbc1f3724
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=522388417 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.522388417 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_384.485721839
Short name T593
Test name
Test status
Simulation time 76756520380 ps
CPU time 1618.45 seconds
Started Mar 24 01:57:52 PM PDT 24
Finished Mar 24 02:24:50 PM PDT 24
Peak memory 335184 kb
Host smart-e3a15a4d-4e26-4f9a-8e30-f646b670a3bd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=485721839 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.485721839 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_sha3_512.3671023867
Short name T353
Test name
Test status
Simulation time 11742852180 ps
CPU time 1290.95 seconds
Started Mar 24 01:57:52 PM PDT 24
Finished Mar 24 02:19:23 PM PDT 24
Peak memory 304552 kb
Host smart-37b1cccc-afcd-4d94-979b-8d1027532272
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3671023867 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.3671023867 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_128.3884328817
Short name T787
Test name
Test status
Simulation time 230430134700 ps
CPU time 5047.07 seconds
Started Mar 24 01:57:52 PM PDT 24
Finished Mar 24 03:21:59 PM PDT 24
Peak memory 658820 kb
Host smart-245d143c-d8ad-4e39-8acd-72079b974085
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3884328817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.3884328817 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/4.kmac_test_vectors_shake_256.3980086233
Short name T709
Test name
Test status
Simulation time 717039444665 ps
CPU time 4805.96 seconds
Started Mar 24 01:57:51 PM PDT 24
Finished Mar 24 03:17:58 PM PDT 24
Peak memory 571924 kb
Host smart-3696c967-7c9f-4e94-b318-6f21e4618db2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3980086233 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.3980086233 +enable_masking=1 +sw_key_masked=0
Directory /workspace/4.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/40.kmac_alert_test.2772385268
Short name T312
Test name
Test status
Simulation time 18941767 ps
CPU time 0.77 seconds
Started Mar 24 02:08:22 PM PDT 24
Finished Mar 24 02:08:23 PM PDT 24
Peak memory 218496 kb
Host smart-2c081e76-1d7a-42b3-a40d-575a681d413a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772385268 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_alert_test.2772385268 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_alert_test/latest

Test location /workspace/coverage/default/40.kmac_app.3231042190
Short name T820
Test name
Test status
Simulation time 737790330 ps
CPU time 44 seconds
Started Mar 24 02:08:10 PM PDT 24
Finished Mar 24 02:08:54 PM PDT 24
Peak memory 226392 kb
Host smart-50b4dca5-6ec2-474e-aeb1-00f8e4181d05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231042190 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_app.3231042190 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_app/latest

Test location /workspace/coverage/default/40.kmac_burst_write.4078445738
Short name T579
Test name
Test status
Simulation time 725503398 ps
CPU time 37.43 seconds
Started Mar 24 02:08:02 PM PDT 24
Finished Mar 24 02:08:40 PM PDT 24
Peak memory 226988 kb
Host smart-cb23ed84-0541-4dfc-9844-bdd146eeffd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078445738 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_burst_write.4078445738 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_burst_write/latest

Test location /workspace/coverage/default/40.kmac_entropy_refresh.166426281
Short name T455
Test name
Test status
Simulation time 6407150459 ps
CPU time 164.96 seconds
Started Mar 24 02:08:18 PM PDT 24
Finished Mar 24 02:11:03 PM PDT 24
Peak memory 239668 kb
Host smart-c42dd6f0-7c7d-41c9-aa61-e5354cfaf5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166426281 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_entropy_refresh.166426281 +enable_masking=1 +sw
_key_masked=0
Directory /workspace/40.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/40.kmac_error.3237723604
Short name T818
Test name
Test status
Simulation time 969886256 ps
CPU time 71.78 seconds
Started Mar 24 02:08:19 PM PDT 24
Finished Mar 24 02:09:31 PM PDT 24
Peak memory 238956 kb
Host smart-fb561bf1-f970-4bf9-a442-690ede16c35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237723604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_error.3237723604 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_error/latest

Test location /workspace/coverage/default/40.kmac_key_error.1158077549
Short name T768
Test name
Test status
Simulation time 959233074 ps
CPU time 2.24 seconds
Started Mar 24 02:08:19 PM PDT 24
Finished Mar 24 02:08:21 PM PDT 24
Peak memory 218540 kb
Host smart-34b1eeef-a47b-4c7e-9cac-e7802d7cf3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158077549 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_key_error.1158077549 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_key_error/latest

Test location /workspace/coverage/default/40.kmac_lc_escalation.2293205426
Short name T1043
Test name
Test status
Simulation time 91642775 ps
CPU time 1.34 seconds
Started Mar 24 02:08:19 PM PDT 24
Finished Mar 24 02:08:20 PM PDT 24
Peak memory 218600 kb
Host smart-658dabd0-4c49-4ca3-b3e3-234d3e0bed3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293205426 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.2293205426 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/40.kmac_lc_escalation/latest

Test location /workspace/coverage/default/40.kmac_long_msg_and_output.586311858
Short name T932
Test name
Test status
Simulation time 9242762952 ps
CPU time 872.11 seconds
Started Mar 24 02:07:57 PM PDT 24
Finished Mar 24 02:22:30 PM PDT 24
Peak memory 302340 kb
Host smart-80b2014e-af71-41e4-a2a7-2e2052edb6c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586311858 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_long_msg_an
d_output.586311858 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/40.kmac_sideload.607733739
Short name T215
Test name
Test status
Simulation time 3687289933 ps
CPU time 149.7 seconds
Started Mar 24 02:07:57 PM PDT 24
Finished Mar 24 02:10:27 PM PDT 24
Peak memory 235552 kb
Host smart-02a9b6f8-ddf8-439f-8a8f-dac55c9b0982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607733739 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload.607733739 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_sideload/latest

Test location /workspace/coverage/default/40.kmac_smoke.1310767919
Short name T269
Test name
Test status
Simulation time 4953055604 ps
CPU time 51.26 seconds
Started Mar 24 02:07:57 PM PDT 24
Finished Mar 24 02:08:49 PM PDT 24
Peak memory 222788 kb
Host smart-f691458c-8805-4501-bfd0-6d4e08af449f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310767919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_smoke.1310767919 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_smoke/latest

Test location /workspace/coverage/default/40.kmac_stress_all.2237969423
Short name T228
Test name
Test status
Simulation time 57682874756 ps
CPU time 425.11 seconds
Started Mar 24 02:08:19 PM PDT 24
Finished Mar 24 02:15:25 PM PDT 24
Peak memory 254904 kb
Host smart-050e85ec-b305-452d-a58c-17eb2a6d2558
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2237969423 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_stress_all.2237969423 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_stress_all/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac.307097181
Short name T911
Test name
Test status
Simulation time 290448093 ps
CPU time 5.37 seconds
Started Mar 24 02:08:06 PM PDT 24
Finished Mar 24 02:08:11 PM PDT 24
Peak memory 218680 kb
Host smart-f785ca63-56b1-448f-aebb-06ab1d1144d2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307097181 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 40.kmac_test_vectors_kmac.307097181 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_kmac_xof.1330799544
Short name T411
Test name
Test status
Simulation time 609210404 ps
CPU time 5.82 seconds
Started Mar 24 02:08:09 PM PDT 24
Finished Mar 24 02:08:15 PM PDT 24
Peak memory 218616 kb
Host smart-e63ba775-210f-4da6-9e74-16c64646f9ef
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330799544 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 40.kmac_test_vectors_kmac_xof.1330799544 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_224.408691756
Short name T389
Test name
Test status
Simulation time 219882737315 ps
CPU time 2021.2 seconds
Started Mar 24 02:08:00 PM PDT 24
Finished Mar 24 02:41:42 PM PDT 24
Peak memory 386792 kb
Host smart-8edbac0d-47c1-498a-966e-d193a4e59a5a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=408691756 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_224.408691756 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_256.4042481765
Short name T1056
Test name
Test status
Simulation time 753355148743 ps
CPU time 2291.12 seconds
Started Mar 24 02:08:01 PM PDT 24
Finished Mar 24 02:46:13 PM PDT 24
Peak memory 376936 kb
Host smart-d1f6caa7-fb54-4e35-9815-1721a735eb8c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4042481765 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_256.4042481765 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_384.1919982925
Short name T836
Test name
Test status
Simulation time 84823663213 ps
CPU time 1776.72 seconds
Started Mar 24 02:08:05 PM PDT 24
Finished Mar 24 02:37:42 PM PDT 24
Peak memory 333740 kb
Host smart-96c7d198-545f-4b76-8eb3-b13cc1f5ada6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1919982925 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_384.1919982925 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_sha3_512.2952795630
Short name T690
Test name
Test status
Simulation time 47094549842 ps
CPU time 1270.35 seconds
Started Mar 24 02:08:05 PM PDT 24
Finished Mar 24 02:29:15 PM PDT 24
Peak memory 304128 kb
Host smart-2812ff29-0785-458d-a2b6-3ccebad81b2d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2952795630 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_sha3_512.2952795630 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_128.1369228618
Short name T624
Test name
Test status
Simulation time 129131038823 ps
CPU time 5549.24 seconds
Started Mar 24 02:08:05 PM PDT 24
Finished Mar 24 03:40:35 PM PDT 24
Peak memory 656136 kb
Host smart-46f66ebc-0feb-46da-9051-22c94495a7d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1369228618 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_128.1369228618 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/40.kmac_test_vectors_shake_256.2216698622
Short name T798
Test name
Test status
Simulation time 110980927418 ps
CPU time 4269.76 seconds
Started Mar 24 02:08:05 PM PDT 24
Finished Mar 24 03:19:16 PM PDT 24
Peak memory 572232 kb
Host smart-74bf8768-51a8-4fc0-a162-579e2c3e3cdc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2216698622 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_test_vectors_shake_256.2216698622 +enable_masking=1 +sw_key_masked=0
Directory /workspace/40.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/41.kmac_alert_test.3684913305
Short name T511
Test name
Test status
Simulation time 204943140 ps
CPU time 0.87 seconds
Started Mar 24 02:08:52 PM PDT 24
Finished Mar 24 02:08:53 PM PDT 24
Peak memory 218476 kb
Host smart-c5cf468f-2b86-4c07-b492-789d6aef20c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684913305 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_alert_test.3684913305 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_alert_test/latest

Test location /workspace/coverage/default/41.kmac_app.2809525593
Short name T991
Test name
Test status
Simulation time 36271900743 ps
CPU time 311.08 seconds
Started Mar 24 02:08:43 PM PDT 24
Finished Mar 24 02:13:54 PM PDT 24
Peak memory 249860 kb
Host smart-a72fcd50-b338-49c1-8bc3-6e76677b587a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809525593 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_app.2809525593 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_app/latest

Test location /workspace/coverage/default/41.kmac_burst_write.1388224628
Short name T131
Test name
Test status
Simulation time 28252934984 ps
CPU time 1043.54 seconds
Started Mar 24 02:08:29 PM PDT 24
Finished Mar 24 02:25:52 PM PDT 24
Peak memory 243192 kb
Host smart-62b85b30-c3ad-47aa-b0d5-22e724c1134a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388224628 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_burst_write.1388224628 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_burst_write/latest

Test location /workspace/coverage/default/41.kmac_entropy_refresh.1975931767
Short name T498
Test name
Test status
Simulation time 5281132542 ps
CPU time 104.99 seconds
Started Mar 24 02:08:44 PM PDT 24
Finished Mar 24 02:10:29 PM PDT 24
Peak memory 235008 kb
Host smart-a41b77c0-3211-4009-bce6-3f64effcd298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975931767 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_entropy_refresh.1975931767 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/41.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/41.kmac_error.2944056286
Short name T566
Test name
Test status
Simulation time 124884067785 ps
CPU time 308.45 seconds
Started Mar 24 02:08:48 PM PDT 24
Finished Mar 24 02:13:57 PM PDT 24
Peak memory 255124 kb
Host smart-b40e3d2a-65a5-4c93-87f4-1536d307f2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944056286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_error.2944056286 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_error/latest

Test location /workspace/coverage/default/41.kmac_key_error.227531064
Short name T309
Test name
Test status
Simulation time 59389458 ps
CPU time 1.22 seconds
Started Mar 24 02:08:50 PM PDT 24
Finished Mar 24 02:08:52 PM PDT 24
Peak memory 222024 kb
Host smart-4dc62a8b-4807-40e0-8ba7-1e7bc13a66ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227531064 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_key_error.227531064 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_key_error/latest

Test location /workspace/coverage/default/41.kmac_lc_escalation.3621747361
Short name T77
Test name
Test status
Simulation time 63232802 ps
CPU time 1.37 seconds
Started Mar 24 02:08:47 PM PDT 24
Finished Mar 24 02:08:49 PM PDT 24
Peak memory 218684 kb
Host smart-0d7a0fda-ef10-48ca-bce8-0479dcb0c7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621747361 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.3621747361 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/41.kmac_lc_escalation/latest

Test location /workspace/coverage/default/41.kmac_long_msg_and_output.75440418
Short name T248
Test name
Test status
Simulation time 14078580449 ps
CPU time 1532.93 seconds
Started Mar 24 02:08:25 PM PDT 24
Finished Mar 24 02:33:58 PM PDT 24
Peak memory 352660 kb
Host smart-beac5b76-2988-4c7a-a814-d12ddca8e3af
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75440418 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_long_msg_and
_output.75440418 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/41.kmac_sideload.2233148660
Short name T387
Test name
Test status
Simulation time 10035358872 ps
CPU time 384.57 seconds
Started Mar 24 02:08:30 PM PDT 24
Finished Mar 24 02:14:56 PM PDT 24
Peak memory 251476 kb
Host smart-853dc795-514b-4eab-869b-99ef4de72564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233148660 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload.2233148660 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_sideload/latest

Test location /workspace/coverage/default/41.kmac_smoke.1075845254
Short name T561
Test name
Test status
Simulation time 6552989128 ps
CPU time 65.3 seconds
Started Mar 24 02:08:22 PM PDT 24
Finished Mar 24 02:09:28 PM PDT 24
Peak memory 226796 kb
Host smart-305a1e33-de43-4872-8ac9-785aa0481ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075845254 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_smoke.1075845254 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_smoke/latest

Test location /workspace/coverage/default/41.kmac_stress_all.4081089296
Short name T903
Test name
Test status
Simulation time 1672689275 ps
CPU time 40.45 seconds
Started Mar 24 02:08:51 PM PDT 24
Finished Mar 24 02:09:32 PM PDT 24
Peak memory 226704 kb
Host smart-b4a42c41-d890-463b-8b57-795767033344
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4081089296 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all.4081089296 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all/latest

Test location /workspace/coverage/default/41.kmac_stress_all_with_rand_reset.5164692
Short name T11
Test name
Test status
Simulation time 56027602983 ps
CPU time 660.63 seconds
Started Mar 24 02:08:52 PM PDT 24
Finished Mar 24 02:19:53 PM PDT 24
Peak memory 298880 kb
Host smart-2d51a203-af0b-41b2-a160-1fda277834c7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=5164692 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_stress_all_with_rand_reset.5164692 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac.407374479
Short name T258
Test name
Test status
Simulation time 437152765 ps
CPU time 6.83 seconds
Started Mar 24 02:08:39 PM PDT 24
Finished Mar 24 02:08:46 PM PDT 24
Peak memory 219544 kb
Host smart-7f517904-0dbb-46ae-8c5b-e3fa4f88983d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407374479 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 41.kmac_test_vectors_kmac.407374479 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_kmac_xof.2231887782
Short name T905
Test name
Test status
Simulation time 426870104 ps
CPU time 5.16 seconds
Started Mar 24 02:08:39 PM PDT 24
Finished Mar 24 02:08:45 PM PDT 24
Peak memory 218644 kb
Host smart-1eb04c6f-261c-4a0b-b8f1-a829da2480d5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231887782 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 41.kmac_test_vectors_kmac_xof.2231887782 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_224.2427227669
Short name T688
Test name
Test status
Simulation time 166900485041 ps
CPU time 2103.82 seconds
Started Mar 24 02:08:30 PM PDT 24
Finished Mar 24 02:43:35 PM PDT 24
Peak memory 390772 kb
Host smart-b91a701d-b0e4-48e9-abd0-afb79f7676fa
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2427227669 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_224.2427227669 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_256.1706960277
Short name T1030
Test name
Test status
Simulation time 19715826981 ps
CPU time 1772.8 seconds
Started Mar 24 02:08:29 PM PDT 24
Finished Mar 24 02:38:02 PM PDT 24
Peak memory 381892 kb
Host smart-44183b55-8c46-4b6d-9a5b-58b20b1581b1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1706960277 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_256.1706960277 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_384.1557900532
Short name T745
Test name
Test status
Simulation time 99059086514 ps
CPU time 1574.78 seconds
Started Mar 24 02:08:34 PM PDT 24
Finished Mar 24 02:34:49 PM PDT 24
Peak memory 341188 kb
Host smart-32b96436-4a9a-484a-8834-b54264ea3908
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1557900532 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_384.1557900532 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_sha3_512.3701801513
Short name T436
Test name
Test status
Simulation time 21262066970 ps
CPU time 1267.58 seconds
Started Mar 24 02:08:37 PM PDT 24
Finished Mar 24 02:29:46 PM PDT 24
Peak memory 296508 kb
Host smart-cc883f3b-9eb9-4a42-8198-9616815a4cb1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3701801513 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_sha3_512.3701801513 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_128.3038091870
Short name T725
Test name
Test status
Simulation time 174483967200 ps
CPU time 5105.26 seconds
Started Mar 24 02:08:35 PM PDT 24
Finished Mar 24 03:33:42 PM PDT 24
Peak memory 637340 kb
Host smart-6aaccb75-6e36-4979-b919-8d1c61c91355
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3038091870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_128.3038091870 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/41.kmac_test_vectors_shake_256.2792882491
Short name T297
Test name
Test status
Simulation time 618188591981 ps
CPU time 5305.45 seconds
Started Mar 24 02:08:40 PM PDT 24
Finished Mar 24 03:37:07 PM PDT 24
Peak memory 560500 kb
Host smart-9d476441-6859-4e46-9c6a-50046eaddd84
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2792882491 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_test_vectors_shake_256.2792882491 +enable_masking=1 +sw_key_masked=0
Directory /workspace/41.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/42.kmac_alert_test.2773981077
Short name T944
Test name
Test status
Simulation time 49214657 ps
CPU time 0.82 seconds
Started Mar 24 02:09:31 PM PDT 24
Finished Mar 24 02:09:32 PM PDT 24
Peak memory 218472 kb
Host smart-cf42864a-3272-471b-9079-20348ea41cce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773981077 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_alert_test.2773981077 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_alert_test/latest

Test location /workspace/coverage/default/42.kmac_app.2728064315
Short name T738
Test name
Test status
Simulation time 59714377847 ps
CPU time 313.86 seconds
Started Mar 24 02:09:25 PM PDT 24
Finished Mar 24 02:14:39 PM PDT 24
Peak memory 246252 kb
Host smart-b5f2be8a-0521-4320-9141-b74d30e672a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728064315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_app.2728064315 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_app/latest

Test location /workspace/coverage/default/42.kmac_burst_write.2822248592
Short name T863
Test name
Test status
Simulation time 14590820054 ps
CPU time 557.05 seconds
Started Mar 24 02:08:55 PM PDT 24
Finished Mar 24 02:18:12 PM PDT 24
Peak memory 233272 kb
Host smart-95b48d37-db55-4e19-a15b-813c5ef02679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822248592 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_burst_write.2822248592 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_burst_write/latest

Test location /workspace/coverage/default/42.kmac_entropy_refresh.2451127915
Short name T563
Test name
Test status
Simulation time 2888055460 ps
CPU time 61.78 seconds
Started Mar 24 02:09:27 PM PDT 24
Finished Mar 24 02:10:30 PM PDT 24
Peak memory 237000 kb
Host smart-5b3e1c0c-3a38-469f-839a-1f4f7c5fcadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451127915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_entropy_refresh.2451127915 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/42.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/42.kmac_error.2814388147
Short name T693
Test name
Test status
Simulation time 1035170939 ps
CPU time 97.86 seconds
Started Mar 24 02:09:25 PM PDT 24
Finished Mar 24 02:11:04 PM PDT 24
Peak memory 243120 kb
Host smart-388d389a-8810-4889-8387-eb1c95a05222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814388147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_error.2814388147 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_error/latest

Test location /workspace/coverage/default/42.kmac_key_error.1945103091
Short name T435
Test name
Test status
Simulation time 1715697602 ps
CPU time 3.36 seconds
Started Mar 24 02:09:26 PM PDT 24
Finished Mar 24 02:09:29 PM PDT 24
Peak memory 218544 kb
Host smart-c2689a8d-97d1-4d07-9057-26ef3d99a0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945103091 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_key_error.1945103091 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_key_error/latest

Test location /workspace/coverage/default/42.kmac_lc_escalation.1867431598
Short name T22
Test name
Test status
Simulation time 2923755050 ps
CPU time 14.97 seconds
Started Mar 24 02:09:27 PM PDT 24
Finished Mar 24 02:09:43 PM PDT 24
Peak memory 235044 kb
Host smart-665f3c45-6390-4fe0-9532-8b1b9a1e28e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867431598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.1867431598 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/42.kmac_lc_escalation/latest

Test location /workspace/coverage/default/42.kmac_long_msg_and_output.1102816792
Short name T736
Test name
Test status
Simulation time 62330348171 ps
CPU time 1398.62 seconds
Started Mar 24 02:08:57 PM PDT 24
Finished Mar 24 02:32:16 PM PDT 24
Peak memory 345136 kb
Host smart-655820fb-4512-49f2-997e-9e14a651c910
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102816792 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_long_msg_a
nd_output.1102816792 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/42.kmac_sideload.3908494961
Short name T520
Test name
Test status
Simulation time 8692989641 ps
CPU time 232.01 seconds
Started Mar 24 02:08:57 PM PDT 24
Finished Mar 24 02:12:49 PM PDT 24
Peak memory 242636 kb
Host smart-a5bfdba4-95ee-457c-a0b8-061d4586068f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908494961 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload.3908494961 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_sideload/latest

Test location /workspace/coverage/default/42.kmac_smoke.484479930
Short name T517
Test name
Test status
Simulation time 895519712 ps
CPU time 34.02 seconds
Started Mar 24 02:08:54 PM PDT 24
Finished Mar 24 02:09:28 PM PDT 24
Peak memory 222472 kb
Host smart-09530fee-1b8a-4a7f-b558-1927bfbddbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484479930 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_smoke.484479930 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_smoke/latest

Test location /workspace/coverage/default/42.kmac_stress_all.3248880322
Short name T425
Test name
Test status
Simulation time 83698388992 ps
CPU time 662.32 seconds
Started Mar 24 02:09:27 PM PDT 24
Finished Mar 24 02:20:30 PM PDT 24
Peak memory 284372 kb
Host smart-b4c18767-297e-4171-96b8-3ddf3063f7b7
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3248880322 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_stress_all.3248880322 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_stress_all/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac.1659286514
Short name T749
Test name
Test status
Simulation time 523766904 ps
CPU time 5.93 seconds
Started Mar 24 02:09:21 PM PDT 24
Finished Mar 24 02:09:27 PM PDT 24
Peak memory 218672 kb
Host smart-ee63084c-e121-4736-9d31-41ee57837b1f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659286514 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 42.kmac_test_vectors_kmac.1659286514 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_kmac_xof.2591472768
Short name T381
Test name
Test status
Simulation time 898553286 ps
CPU time 6.88 seconds
Started Mar 24 02:09:20 PM PDT 24
Finished Mar 24 02:09:27 PM PDT 24
Peak memory 226712 kb
Host smart-497775e1-e543-4ffb-9bc4-69ad130adfd9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591472768 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 42.kmac_test_vectors_kmac_xof.2591472768 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_224.2368488338
Short name T413
Test name
Test status
Simulation time 267412832889 ps
CPU time 2304.75 seconds
Started Mar 24 02:08:56 PM PDT 24
Finished Mar 24 02:47:21 PM PDT 24
Peak memory 404452 kb
Host smart-3c139607-cbdf-4958-9951-66c6750ac22f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2368488338 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_224.2368488338 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_256.3730701454
Short name T221
Test name
Test status
Simulation time 92528650726 ps
CPU time 2206.94 seconds
Started Mar 24 02:09:02 PM PDT 24
Finished Mar 24 02:45:49 PM PDT 24
Peak memory 376716 kb
Host smart-9bf6671e-2d5a-4411-91aa-2eb192b0326d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3730701454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_256.3730701454 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_384.1439989983
Short name T710
Test name
Test status
Simulation time 18457359144 ps
CPU time 1545.92 seconds
Started Mar 24 02:09:04 PM PDT 24
Finished Mar 24 02:34:51 PM PDT 24
Peak memory 343152 kb
Host smart-8fdecda6-dd21-4b89-8826-73fe4b31b3d7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1439989983 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_384.1439989983 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_sha3_512.419705545
Short name T713
Test name
Test status
Simulation time 44179662166 ps
CPU time 1148.18 seconds
Started Mar 24 02:09:11 PM PDT 24
Finished Mar 24 02:28:19 PM PDT 24
Peak memory 303480 kb
Host smart-5809b673-9d4f-4f32-a5b4-34e6731c015e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=419705545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_sha3_512.419705545 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/42.kmac_test_vectors_shake_256.2797373724
Short name T417
Test name
Test status
Simulation time 779812744660 ps
CPU time 5049.78 seconds
Started Mar 24 02:09:15 PM PDT 24
Finished Mar 24 03:33:25 PM PDT 24
Peak memory 579432 kb
Host smart-f2af9f66-bb03-4117-9cba-b97b5289e3be
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2797373724 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_test_vectors_shake_256.2797373724 +enable_masking=1 +sw_key_masked=0
Directory /workspace/42.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/43.kmac_alert_test.3506806081
Short name T872
Test name
Test status
Simulation time 49450680 ps
CPU time 0.82 seconds
Started Mar 24 02:10:07 PM PDT 24
Finished Mar 24 02:10:08 PM PDT 24
Peak memory 218732 kb
Host smart-21fb03c3-70ea-426b-b511-18b708b9287d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506806081 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_alert_test.3506806081 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_alert_test/latest

Test location /workspace/coverage/default/43.kmac_app.1618084060
Short name T841
Test name
Test status
Simulation time 20386553003 ps
CPU time 320.87 seconds
Started Mar 24 02:10:05 PM PDT 24
Finished Mar 24 02:15:26 PM PDT 24
Peak memory 246952 kb
Host smart-03d50c33-d8af-43d1-82ff-9224de0f66af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618084060 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_app.1618084060 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_app/latest

Test location /workspace/coverage/default/43.kmac_burst_write.788541042
Short name T694
Test name
Test status
Simulation time 13131422822 ps
CPU time 1275.56 seconds
Started Mar 24 02:09:36 PM PDT 24
Finished Mar 24 02:30:51 PM PDT 24
Peak memory 237840 kb
Host smart-1897bf38-144d-4f05-beb2-ea76fe9dea8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788541042 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_burst_write.788541042 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_burst_write/latest

Test location /workspace/coverage/default/43.kmac_entropy_refresh.1720346239
Short name T887
Test name
Test status
Simulation time 5264918139 ps
CPU time 125.34 seconds
Started Mar 24 02:10:02 PM PDT 24
Finished Mar 24 02:12:07 PM PDT 24
Peak memory 234276 kb
Host smart-c6b4acd1-bfe1-440d-8cbd-27104394eba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720346239 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_entropy_refresh.1720346239 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/43.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/43.kmac_error.2542797598
Short name T321
Test name
Test status
Simulation time 12659295213 ps
CPU time 313.75 seconds
Started Mar 24 02:10:05 PM PDT 24
Finished Mar 24 02:15:19 PM PDT 24
Peak memory 251956 kb
Host smart-3254b6ea-481b-46d7-8768-00d80f910db7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542797598 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_error.2542797598 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_error/latest

Test location /workspace/coverage/default/43.kmac_key_error.2594686180
Short name T915
Test name
Test status
Simulation time 1895360918 ps
CPU time 3.28 seconds
Started Mar 24 02:10:04 PM PDT 24
Finished Mar 24 02:10:08 PM PDT 24
Peak memory 218588 kb
Host smart-bf26b1af-e8b7-4966-a941-b778b3fe14eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594686180 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_key_error.2594686180 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_key_error/latest

Test location /workspace/coverage/default/43.kmac_lc_escalation.752542880
Short name T28
Test name
Test status
Simulation time 62304125 ps
CPU time 1.54 seconds
Started Mar 24 02:10:06 PM PDT 24
Finished Mar 24 02:10:08 PM PDT 24
Peak memory 219484 kb
Host smart-703f5c86-0868-479e-bb5d-ea926989f5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752542880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.752542880 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/43.kmac_lc_escalation/latest

Test location /workspace/coverage/default/43.kmac_long_msg_and_output.2407013063
Short name T319
Test name
Test status
Simulation time 42471762727 ps
CPU time 1050.52 seconds
Started Mar 24 02:09:29 PM PDT 24
Finished Mar 24 02:27:00 PM PDT 24
Peak memory 307868 kb
Host smart-ae716f1d-cbe5-4758-a6eb-f4f565689b29
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407013063 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_long_msg_a
nd_output.2407013063 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/43.kmac_sideload.2784557191
Short name T762
Test name
Test status
Simulation time 8751016368 ps
CPU time 67.78 seconds
Started Mar 24 02:09:35 PM PDT 24
Finished Mar 24 02:10:43 PM PDT 24
Peak memory 226224 kb
Host smart-b278b5c6-b331-4872-b562-5045ec1f82ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784557191 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload.2784557191 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_sideload/latest

Test location /workspace/coverage/default/43.kmac_smoke.1245667757
Short name T482
Test name
Test status
Simulation time 3234012125 ps
CPU time 67.34 seconds
Started Mar 24 02:09:30 PM PDT 24
Finished Mar 24 02:10:38 PM PDT 24
Peak memory 221848 kb
Host smart-714933d1-97a8-408a-8163-ba1831564011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245667757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_smoke.1245667757 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_smoke/latest

Test location /workspace/coverage/default/43.kmac_stress_all.2138303829
Short name T810
Test name
Test status
Simulation time 72244775192 ps
CPU time 460.75 seconds
Started Mar 24 02:10:07 PM PDT 24
Finished Mar 24 02:17:48 PM PDT 24
Peak memory 271240 kb
Host smart-e37661c4-9d32-4aa7-8412-684ebb6b8672
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2138303829 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_stress_all.2138303829 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_stress_all/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac.23274666
Short name T892
Test name
Test status
Simulation time 4343321962 ps
CPU time 8.42 seconds
Started Mar 24 02:10:03 PM PDT 24
Finished Mar 24 02:10:11 PM PDT 24
Peak memory 218672 kb
Host smart-b3092720-c04f-41cb-842b-1db81be06a4e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23274666 -assert nopostproc +UVM_TESTNAME=kmac_base_t
est +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n
ull -cm_name 43.kmac_test_vectors_kmac.23274666 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_kmac_xof.1236093903
Short name T366
Test name
Test status
Simulation time 460350215 ps
CPU time 6.62 seconds
Started Mar 24 02:10:02 PM PDT 24
Finished Mar 24 02:10:08 PM PDT 24
Peak memory 219588 kb
Host smart-f8ac6385-3950-4a5d-9938-dc41586f899e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236093903 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 43.kmac_test_vectors_kmac_xof.1236093903 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_224.2222251501
Short name T185
Test name
Test status
Simulation time 20405605372 ps
CPU time 1902.17 seconds
Started Mar 24 02:09:40 PM PDT 24
Finished Mar 24 02:41:22 PM PDT 24
Peak memory 399648 kb
Host smart-90051596-1adb-4f39-8802-0f90045235bb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2222251501 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_224.2222251501 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_256.543298744
Short name T981
Test name
Test status
Simulation time 83260190882 ps
CPU time 2183.01 seconds
Started Mar 24 02:09:44 PM PDT 24
Finished Mar 24 02:46:07 PM PDT 24
Peak memory 388156 kb
Host smart-2ce75d4f-eb2a-4582-9586-6a2c83e64321
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=543298744 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_256.543298744 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_384.4042711364
Short name T370
Test name
Test status
Simulation time 69875387329 ps
CPU time 1731.23 seconds
Started Mar 24 02:09:44 PM PDT 24
Finished Mar 24 02:38:36 PM PDT 24
Peak memory 337504 kb
Host smart-b90a5975-e70d-4ea8-9e8f-99d1ff091798
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4042711364 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_384.4042711364 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_sha3_512.1742342665
Short name T1036
Test name
Test status
Simulation time 139184121731 ps
CPU time 1353.17 seconds
Started Mar 24 02:09:47 PM PDT 24
Finished Mar 24 02:32:21 PM PDT 24
Peak memory 300940 kb
Host smart-a8d1046c-c48e-4298-bf3c-81743c3fca99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1742342665 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_sha3_512.1742342665 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_128.4278398348
Short name T889
Test name
Test status
Simulation time 291967143286 ps
CPU time 6495.66 seconds
Started Mar 24 02:09:58 PM PDT 24
Finished Mar 24 03:58:15 PM PDT 24
Peak memory 671436 kb
Host smart-4ef3be61-f4f7-4703-b6ac-59392ec753db
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=4278398348 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_128.4278398348 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/43.kmac_test_vectors_shake_256.3494030010
Short name T237
Test name
Test status
Simulation time 158308764706 ps
CPU time 5059.96 seconds
Started Mar 24 02:09:57 PM PDT 24
Finished Mar 24 03:34:18 PM PDT 24
Peak memory 573756 kb
Host smart-73f1d855-9f3d-42f9-8a29-e622336700f0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3494030010 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_test_vectors_shake_256.3494030010 +enable_masking=1 +sw_key_masked=0
Directory /workspace/43.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/44.kmac_alert_test.2927781123
Short name T819
Test name
Test status
Simulation time 69464897 ps
CPU time 0.84 seconds
Started Mar 24 02:10:45 PM PDT 24
Finished Mar 24 02:10:46 PM PDT 24
Peak memory 220516 kb
Host smart-92788d61-927a-4332-8ea3-fc957f67cb7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927781123 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_alert_test.2927781123 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_alert_test/latest

Test location /workspace/coverage/default/44.kmac_app.3781156147
Short name T500
Test name
Test status
Simulation time 3431218644 ps
CPU time 83.13 seconds
Started Mar 24 02:10:41 PM PDT 24
Finished Mar 24 02:12:04 PM PDT 24
Peak memory 231096 kb
Host smart-eeac29d1-bdef-4e01-9f28-8c830d8c7f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781156147 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_app.3781156147 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_app/latest

Test location /workspace/coverage/default/44.kmac_burst_write.560356919
Short name T518
Test name
Test status
Simulation time 14942834161 ps
CPU time 669.56 seconds
Started Mar 24 02:10:23 PM PDT 24
Finished Mar 24 02:21:33 PM PDT 24
Peak memory 234520 kb
Host smart-6a6368eb-dbf3-4ede-81c6-65303d4e455d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560356919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_burst_write.560356919 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_burst_write/latest

Test location /workspace/coverage/default/44.kmac_entropy_refresh.3941264120
Short name T1011
Test name
Test status
Simulation time 87980439479 ps
CPU time 408.37 seconds
Started Mar 24 02:10:41 PM PDT 24
Finished Mar 24 02:17:29 PM PDT 24
Peak memory 251156 kb
Host smart-b54588d9-7ad5-4433-9ffd-386137f915ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941264120 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_entropy_refresh.3941264120 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/44.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/44.kmac_error.1473556895
Short name T590
Test name
Test status
Simulation time 10832425252 ps
CPU time 94.65 seconds
Started Mar 24 02:10:47 PM PDT 24
Finished Mar 24 02:12:22 PM PDT 24
Peak memory 243148 kb
Host smart-11acfa0d-56c2-48b9-b161-6809ab373761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473556895 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_error.1473556895 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_error/latest

Test location /workspace/coverage/default/44.kmac_key_error.2528545915
Short name T868
Test name
Test status
Simulation time 2792872903 ps
CPU time 6.27 seconds
Started Mar 24 02:10:45 PM PDT 24
Finished Mar 24 02:10:51 PM PDT 24
Peak memory 218632 kb
Host smart-d1493328-8393-4925-8469-66ed45ea27ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528545915 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_key_error.2528545915 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_key_error/latest

Test location /workspace/coverage/default/44.kmac_long_msg_and_output.2095646699
Short name T907
Test name
Test status
Simulation time 30228344513 ps
CPU time 1544.99 seconds
Started Mar 24 02:10:21 PM PDT 24
Finished Mar 24 02:36:06 PM PDT 24
Peak memory 355476 kb
Host smart-f7ffc99a-43ce-4db8-ae3a-64a866500e57
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095646699 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_long_msg_a
nd_output.2095646699 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/44.kmac_stress_all.1767619139
Short name T416
Test name
Test status
Simulation time 41400848246 ps
CPU time 1126.11 seconds
Started Mar 24 02:10:46 PM PDT 24
Finished Mar 24 02:29:32 PM PDT 24
Peak memory 317204 kb
Host smart-80d60997-f1ee-4033-8534-0b6fbc56b6fb
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1767619139 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_stress_all.1767619139 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_stress_all/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac.1671811762
Short name T212
Test name
Test status
Simulation time 246830947 ps
CPU time 7.05 seconds
Started Mar 24 02:10:31 PM PDT 24
Finished Mar 24 02:10:39 PM PDT 24
Peak memory 226780 kb
Host smart-717fdcf3-254e-44fb-be7a-482dc5d6652f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671811762 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 44.kmac_test_vectors_kmac.1671811762 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_kmac_xof.233352981
Short name T242
Test name
Test status
Simulation time 440319704 ps
CPU time 6.83 seconds
Started Mar 24 02:10:32 PM PDT 24
Finished Mar 24 02:10:40 PM PDT 24
Peak memory 226692 kb
Host smart-c877bca3-7ff6-49be-9fff-588201eefd0a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233352981 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 44.kmac_test_vectors_kmac_xof.233352981 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_224.769933101
Short name T585
Test name
Test status
Simulation time 42191862938 ps
CPU time 1849.56 seconds
Started Mar 24 02:10:23 PM PDT 24
Finished Mar 24 02:41:13 PM PDT 24
Peak memory 389084 kb
Host smart-b72f8a5c-9d2b-4a9a-a768-087fb6bc0c9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=769933101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_224.769933101 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_256.2091768272
Short name T949
Test name
Test status
Simulation time 95014559585 ps
CPU time 2189.4 seconds
Started Mar 24 02:10:24 PM PDT 24
Finished Mar 24 02:46:54 PM PDT 24
Peak memory 383252 kb
Host smart-e16c098e-ec5a-40e7-a3f9-06b643dfcdde
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2091768272 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_256.2091768272 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_384.4017946608
Short name T450
Test name
Test status
Simulation time 74802290375 ps
CPU time 1709.46 seconds
Started Mar 24 02:10:27 PM PDT 24
Finished Mar 24 02:38:57 PM PDT 24
Peak memory 342276 kb
Host smart-e9fece29-8b30-44ca-86b8-d8b9337d8c1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4017946608 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_384.4017946608 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_sha3_512.1874458484
Short name T733
Test name
Test status
Simulation time 33738418676 ps
CPU time 1253.2 seconds
Started Mar 24 02:10:27 PM PDT 24
Finished Mar 24 02:31:21 PM PDT 24
Peak memory 297384 kb
Host smart-223cc177-0d2f-4db7-a314-4e5fb5c7a398
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1874458484 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_sha3_512.1874458484 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_128.1895588452
Short name T598
Test name
Test status
Simulation time 118733678394 ps
CPU time 5130.99 seconds
Started Mar 24 02:10:29 PM PDT 24
Finished Mar 24 03:36:01 PM PDT 24
Peak memory 665892 kb
Host smart-d7c43f5f-c39e-4414-8ece-ba391a6f182d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1895588452 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_128.1895588452 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/44.kmac_test_vectors_shake_256.2995111768
Short name T336
Test name
Test status
Simulation time 197415940207 ps
CPU time 4770.21 seconds
Started Mar 24 02:10:33 PM PDT 24
Finished Mar 24 03:30:04 PM PDT 24
Peak memory 567236 kb
Host smart-bcab95c8-3f95-4827-9fe7-ff1641940345
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2995111768 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_test_vectors_shake_256.2995111768 +enable_masking=1 +sw_key_masked=0
Directory /workspace/44.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/45.kmac_alert_test.2735420770
Short name T177
Test name
Test status
Simulation time 84183307 ps
CPU time 0.81 seconds
Started Mar 24 02:11:13 PM PDT 24
Finished Mar 24 02:11:14 PM PDT 24
Peak memory 218820 kb
Host smart-19f5ccf3-e5b3-440a-a4bc-cb86a35a791c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2735420770 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_alert_test.2735420770 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_alert_test/latest

Test location /workspace/coverage/default/45.kmac_app.4076550994
Short name T1078
Test name
Test status
Simulation time 9967551402 ps
CPU time 371.72 seconds
Started Mar 24 02:11:05 PM PDT 24
Finished Mar 24 02:17:17 PM PDT 24
Peak memory 250224 kb
Host smart-415685e3-e954-4d57-a9a7-b9749d5f2ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076550994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_app.4076550994 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_app/latest

Test location /workspace/coverage/default/45.kmac_burst_write.3212538974
Short name T99
Test name
Test status
Simulation time 9341484299 ps
CPU time 914.96 seconds
Started Mar 24 02:10:46 PM PDT 24
Finished Mar 24 02:26:01 PM PDT 24
Peak memory 243192 kb
Host smart-7bddc40d-2101-4112-9df7-77afcf3429cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212538974 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_burst_write.3212538974 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_burst_write/latest

Test location /workspace/coverage/default/45.kmac_error.2230825071
Short name T689
Test name
Test status
Simulation time 116436854035 ps
CPU time 445.47 seconds
Started Mar 24 02:11:04 PM PDT 24
Finished Mar 24 02:18:30 PM PDT 24
Peak memory 259516 kb
Host smart-cc91c077-f5ef-446d-bc1d-6165240e148a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230825071 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_error.2230825071 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_error/latest

Test location /workspace/coverage/default/45.kmac_key_error.3441335819
Short name T899
Test name
Test status
Simulation time 2076188341 ps
CPU time 3.63 seconds
Started Mar 24 02:11:05 PM PDT 24
Finished Mar 24 02:11:08 PM PDT 24
Peak memory 218556 kb
Host smart-74718440-f61a-48d1-9a09-3c6548e91574
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441335819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_key_error.3441335819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_key_error/latest

Test location /workspace/coverage/default/45.kmac_lc_escalation.1982689246
Short name T1023
Test name
Test status
Simulation time 43768660 ps
CPU time 1.27 seconds
Started Mar 24 02:11:03 PM PDT 24
Finished Mar 24 02:11:05 PM PDT 24
Peak memory 218664 kb
Host smart-635658e6-156f-4fba-9e8a-93d132b8f3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982689246 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.1982689246 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/45.kmac_lc_escalation/latest

Test location /workspace/coverage/default/45.kmac_long_msg_and_output.1608776372
Short name T861
Test name
Test status
Simulation time 107386951596 ps
CPU time 1815.15 seconds
Started Mar 24 02:10:46 PM PDT 24
Finished Mar 24 02:41:02 PM PDT 24
Peak memory 363500 kb
Host smart-ba7a7018-7f6e-4c08-9c77-e5d0ccc55640
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608776372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_long_msg_a
nd_output.1608776372 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/45.kmac_sideload.3252062866
Short name T545
Test name
Test status
Simulation time 3268636979 ps
CPU time 82.63 seconds
Started Mar 24 02:10:46 PM PDT 24
Finished Mar 24 02:12:08 PM PDT 24
Peak memory 230044 kb
Host smart-0bd917d7-b7e0-46f2-b17b-b137f56bc288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252062866 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload.3252062866 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_sideload/latest

Test location /workspace/coverage/default/45.kmac_smoke.1767514372
Short name T853
Test name
Test status
Simulation time 5126860595 ps
CPU time 39.77 seconds
Started Mar 24 02:10:45 PM PDT 24
Finished Mar 24 02:11:25 PM PDT 24
Peak memory 223268 kb
Host smart-dce9a1e6-cfe1-40d5-9358-8b01e41c6be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767514372 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_smoke.1767514372 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_smoke/latest

Test location /workspace/coverage/default/45.kmac_stress_all.769958116
Short name T632
Test name
Test status
Simulation time 34012035684 ps
CPU time 744.18 seconds
Started Mar 24 02:11:15 PM PDT 24
Finished Mar 24 02:23:40 PM PDT 24
Peak memory 269584 kb
Host smart-f1f7a668-6431-45c7-a0a3-fa2bd8633e44
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=769958116 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_stress_all.769958116 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_stress_all/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac.2174862433
Short name T866
Test name
Test status
Simulation time 875893919 ps
CPU time 6.13 seconds
Started Mar 24 02:10:59 PM PDT 24
Finished Mar 24 02:11:05 PM PDT 24
Peak memory 218672 kb
Host smart-69c91e2a-46de-4d2a-8399-37f5b4987d76
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174862433 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 45.kmac_test_vectors_kmac.2174862433 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_kmac_xof.1371855841
Short name T325
Test name
Test status
Simulation time 938698637 ps
CPU time 6.17 seconds
Started Mar 24 02:11:00 PM PDT 24
Finished Mar 24 02:11:07 PM PDT 24
Peak memory 226720 kb
Host smart-ffb404b9-466b-4de8-b0b5-bb8de54bd469
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371855841 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 45.kmac_test_vectors_kmac_xof.1371855841 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_224.2188297450
Short name T748
Test name
Test status
Simulation time 233047352745 ps
CPU time 2232.21 seconds
Started Mar 24 02:10:51 PM PDT 24
Finished Mar 24 02:48:03 PM PDT 24
Peak memory 395212 kb
Host smart-f8970cd7-3807-4c3d-aa8e-83ca843b33f5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2188297450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_224.2188297450 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_256.3889632069
Short name T504
Test name
Test status
Simulation time 1210525164719 ps
CPU time 2320.42 seconds
Started Mar 24 02:10:50 PM PDT 24
Finished Mar 24 02:49:31 PM PDT 24
Peak memory 378632 kb
Host smart-24a6cca1-4857-4b48-9bb7-7078022707de
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3889632069 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_256.3889632069 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_384.3762194902
Short name T106
Test name
Test status
Simulation time 50791679555 ps
CPU time 1697.72 seconds
Started Mar 24 02:10:51 PM PDT 24
Finished Mar 24 02:39:09 PM PDT 24
Peak memory 341212 kb
Host smart-ac55d3a3-6b72-43cd-8d3c-8306bfb935a6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3762194902 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_384.3762194902 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_sha3_512.847844427
Short name T303
Test name
Test status
Simulation time 21446560473 ps
CPU time 1180.49 seconds
Started Mar 24 02:10:51 PM PDT 24
Finished Mar 24 02:30:32 PM PDT 24
Peak memory 295328 kb
Host smart-f6215196-e596-42c8-b3e1-c553b1fbb13d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=847844427 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_sha3_512.847844427 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_128.1606556604
Short name T1070
Test name
Test status
Simulation time 389396990121 ps
CPU time 5181.97 seconds
Started Mar 24 02:10:57 PM PDT 24
Finished Mar 24 03:37:19 PM PDT 24
Peak memory 647560 kb
Host smart-d7d8db92-3fdc-4bbf-bdad-97606004dca6
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1606556604 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_128.1606556604 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/45.kmac_test_vectors_shake_256.2492657308
Short name T771
Test name
Test status
Simulation time 138183282480 ps
CPU time 4759.08 seconds
Started Mar 24 02:10:56 PM PDT 24
Finished Mar 24 03:30:16 PM PDT 24
Peak memory 577884 kb
Host smart-31b721b3-80d9-4915-a1a4-9423f1b17229
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2492657308 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_test_vectors_shake_256.2492657308 +enable_masking=1 +sw_key_masked=0
Directory /workspace/45.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/46.kmac_alert_test.205347763
Short name T548
Test name
Test status
Simulation time 31480306 ps
CPU time 0.92 seconds
Started Mar 24 02:11:44 PM PDT 24
Finished Mar 24 02:11:46 PM PDT 24
Peak memory 218496 kb
Host smart-46fdf39f-c55d-49ef-8006-eb7b2d5c0ce3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205347763 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_alert_test.205347763 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/46.kmac_alert_test/latest

Test location /workspace/coverage/default/46.kmac_app.2935631955
Short name T830
Test name
Test status
Simulation time 4208569967 ps
CPU time 95.02 seconds
Started Mar 24 02:11:42 PM PDT 24
Finished Mar 24 02:13:17 PM PDT 24
Peak memory 231852 kb
Host smart-be4d6dd4-c086-4422-ac08-4e4b11f793c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935631955 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_app.2935631955 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_app/latest

Test location /workspace/coverage/default/46.kmac_burst_write.2971195855
Short name T481
Test name
Test status
Simulation time 10180187277 ps
CPU time 509.25 seconds
Started Mar 24 02:11:19 PM PDT 24
Finished Mar 24 02:19:48 PM PDT 24
Peak memory 232780 kb
Host smart-6897b639-d842-4971-8b76-d69c3d4927a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971195855 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_burst_write.2971195855 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_burst_write/latest

Test location /workspace/coverage/default/46.kmac_entropy_refresh.3451356412
Short name T1029
Test name
Test status
Simulation time 10632032213 ps
CPU time 206.78 seconds
Started Mar 24 02:11:39 PM PDT 24
Finished Mar 24 02:15:06 PM PDT 24
Peak memory 243112 kb
Host smart-6428b88a-bf16-4c90-8d9f-f18de00cafcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451356412 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_entropy_refresh.3451356412 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/46.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/46.kmac_error.70432110
Short name T533
Test name
Test status
Simulation time 1731737772 ps
CPU time 50.2 seconds
Started Mar 24 02:11:40 PM PDT 24
Finished Mar 24 02:12:30 PM PDT 24
Peak memory 243320 kb
Host smart-1aab53f4-7c3a-4b0d-9ece-d031da6ccb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70432110 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_error.70432110 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_error/latest

Test location /workspace/coverage/default/46.kmac_key_error.4072738951
Short name T445
Test name
Test status
Simulation time 490712678 ps
CPU time 3.12 seconds
Started Mar 24 02:11:40 PM PDT 24
Finished Mar 24 02:11:43 PM PDT 24
Peak memory 218536 kb
Host smart-c05ceb5c-80e5-46d8-88ad-bbdfeba0e3a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072738951 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_key_error.4072738951 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_key_error/latest

Test location /workspace/coverage/default/46.kmac_lc_escalation.4122521551
Short name T1012
Test name
Test status
Simulation time 148013899 ps
CPU time 1.25 seconds
Started Mar 24 02:11:42 PM PDT 24
Finished Mar 24 02:11:43 PM PDT 24
Peak memory 218580 kb
Host smart-3c521e94-3ef7-4de2-8bd7-2a024cb44134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122521551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.4122521551 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/46.kmac_lc_escalation/latest

Test location /workspace/coverage/default/46.kmac_long_msg_and_output.3386050201
Short name T822
Test name
Test status
Simulation time 69633678033 ps
CPU time 1895.78 seconds
Started Mar 24 02:11:14 PM PDT 24
Finished Mar 24 02:42:50 PM PDT 24
Peak memory 391188 kb
Host smart-567dba02-b4ba-4d9d-b7f7-caf700256746
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386050201 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_long_msg_a
nd_output.3386050201 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/46.kmac_sideload.4146240171
Short name T782
Test name
Test status
Simulation time 2470794585 ps
CPU time 49.18 seconds
Started Mar 24 02:11:13 PM PDT 24
Finished Mar 24 02:12:03 PM PDT 24
Peak memory 226840 kb
Host smart-a281ceee-86bb-40d6-9124-8126e4785ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146240171 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload.4146240171 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_sideload/latest

Test location /workspace/coverage/default/46.kmac_smoke.2126936175
Short name T978
Test name
Test status
Simulation time 1271046351 ps
CPU time 45.7 seconds
Started Mar 24 02:11:13 PM PDT 24
Finished Mar 24 02:11:59 PM PDT 24
Peak memory 226620 kb
Host smart-54cb665e-facf-4c57-adfe-3bcf63eb664b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126936175 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_smoke.2126936175 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_smoke/latest

Test location /workspace/coverage/default/46.kmac_stress_all.4126974772
Short name T346
Test name
Test status
Simulation time 56888924138 ps
CPU time 972.21 seconds
Started Mar 24 02:11:40 PM PDT 24
Finished Mar 24 02:27:52 PM PDT 24
Peak memory 335364 kb
Host smart-bc971539-f2cf-43a8-b844-2a5f775345c9
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4126974772 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_stress_all.4126974772 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_stress_all/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac.4155964089
Short name T475
Test name
Test status
Simulation time 205488904 ps
CPU time 5.75 seconds
Started Mar 24 02:11:31 PM PDT 24
Finished Mar 24 02:11:37 PM PDT 24
Peak memory 226732 kb
Host smart-b7956398-0d6d-4872-b79d-de8429bcef37
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155964089 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 46.kmac_test_vectors_kmac.4155964089 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_kmac_xof.3240236732
Short name T348
Test name
Test status
Simulation time 386693219 ps
CPU time 6.47 seconds
Started Mar 24 02:11:34 PM PDT 24
Finished Mar 24 02:11:41 PM PDT 24
Peak memory 226968 kb
Host smart-199346fc-b85b-4585-a459-3a336b167bdd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240236732 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 46.kmac_test_vectors_kmac_xof.3240236732 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_224.1960041294
Short name T429
Test name
Test status
Simulation time 272310473920 ps
CPU time 2246.26 seconds
Started Mar 24 02:11:19 PM PDT 24
Finished Mar 24 02:48:46 PM PDT 24
Peak memory 395844 kb
Host smart-7256af4b-e73a-4752-b41f-1453d39dfa3f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1960041294 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_224.1960041294 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_256.3787740486
Short name T631
Test name
Test status
Simulation time 52666568138 ps
CPU time 2109.37 seconds
Started Mar 24 02:11:18 PM PDT 24
Finished Mar 24 02:46:28 PM PDT 24
Peak memory 385988 kb
Host smart-8957b0f3-33db-4c08-8c22-6df011a206cd
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3787740486 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_256.3787740486 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_384.2532928435
Short name T717
Test name
Test status
Simulation time 199897965650 ps
CPU time 1656.85 seconds
Started Mar 24 02:11:23 PM PDT 24
Finished Mar 24 02:39:01 PM PDT 24
Peak memory 342448 kb
Host smart-1b2453b2-ade0-4d84-a3a7-dca26571fdbf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2532928435 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_384.2532928435 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_sha3_512.618790518
Short name T666
Test name
Test status
Simulation time 89294770497 ps
CPU time 1255.29 seconds
Started Mar 24 02:11:24 PM PDT 24
Finished Mar 24 02:32:20 PM PDT 24
Peak memory 300624 kb
Host smart-c7d25d0a-1cd7-4019-b3e7-6a23c6835367
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=618790518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_sha3_512.618790518 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_128.1960806781
Short name T849
Test name
Test status
Simulation time 362143230723 ps
CPU time 5591.57 seconds
Started Mar 24 02:11:24 PM PDT 24
Finished Mar 24 03:44:37 PM PDT 24
Peak memory 637852 kb
Host smart-2b426191-c9e7-45ca-88bf-381bf7d6db36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1960806781 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_128.1960806781 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/46.kmac_test_vectors_shake_256.1861004836
Short name T422
Test name
Test status
Simulation time 433738309045 ps
CPU time 5379.5 seconds
Started Mar 24 02:11:24 PM PDT 24
Finished Mar 24 03:41:04 PM PDT 24
Peak memory 562124 kb
Host smart-bcee1a08-38b7-40e1-836c-f4c13f7efbda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1861004836 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_test_vectors_shake_256.1861004836 +enable_masking=1 +sw_key_masked=0
Directory /workspace/46.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/47.kmac_alert_test.1507736817
Short name T176
Test name
Test status
Simulation time 56860967 ps
CPU time 0.84 seconds
Started Mar 24 02:12:17 PM PDT 24
Finished Mar 24 02:12:18 PM PDT 24
Peak memory 220516 kb
Host smart-d5e8dde5-7da4-4eb4-8b36-19b880c1b132
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507736817 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_alert_test.1507736817 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_alert_test/latest

Test location /workspace/coverage/default/47.kmac_app.990966776
Short name T746
Test name
Test status
Simulation time 2110364744 ps
CPU time 128.52 seconds
Started Mar 24 02:12:02 PM PDT 24
Finished Mar 24 02:14:12 PM PDT 24
Peak memory 236540 kb
Host smart-b59dcb59-9f32-4773-b756-821e25d689d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990966776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_app.990966776 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_app/latest

Test location /workspace/coverage/default/47.kmac_burst_write.2974278100
Short name T284
Test name
Test status
Simulation time 8663691998 ps
CPU time 343.64 seconds
Started Mar 24 02:11:49 PM PDT 24
Finished Mar 24 02:17:33 PM PDT 24
Peak memory 230140 kb
Host smart-44e45491-60ec-43e9-ba04-df4628c3c5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2974278100 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_burst_write.2974278100 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_burst_write/latest

Test location /workspace/coverage/default/47.kmac_entropy_refresh.2911022927
Short name T723
Test name
Test status
Simulation time 12534516044 ps
CPU time 74.82 seconds
Started Mar 24 02:12:08 PM PDT 24
Finished Mar 24 02:13:23 PM PDT 24
Peak memory 234976 kb
Host smart-a316c143-5d22-4be2-b778-cd486efebf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911022927 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_entropy_refresh.2911022927 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/47.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/47.kmac_error.2189351439
Short name T391
Test name
Test status
Simulation time 12403368094 ps
CPU time 274.63 seconds
Started Mar 24 02:12:08 PM PDT 24
Finished Mar 24 02:16:43 PM PDT 24
Peak memory 259536 kb
Host smart-5b12ec20-3123-4f6b-8886-246307eb4d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189351439 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_error.2189351439 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_error/latest

Test location /workspace/coverage/default/47.kmac_key_error.491112039
Short name T102
Test name
Test status
Simulation time 934746890 ps
CPU time 5.77 seconds
Started Mar 24 02:12:12 PM PDT 24
Finished Mar 24 02:12:18 PM PDT 24
Peak memory 218476 kb
Host smart-9cf6f8ce-d162-4308-b599-90706d99912a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491112039 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_key_error.491112039 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_key_error/latest

Test location /workspace/coverage/default/47.kmac_lc_escalation.174604681
Short name T26
Test name
Test status
Simulation time 148247707 ps
CPU time 1.31 seconds
Started Mar 24 02:12:18 PM PDT 24
Finished Mar 24 02:12:20 PM PDT 24
Peak memory 218604 kb
Host smart-e2488e10-749d-4e70-bcaf-5b00b562f611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174604681 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.174604681 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/47.kmac_lc_escalation/latest

Test location /workspace/coverage/default/47.kmac_long_msg_and_output.128902138
Short name T828
Test name
Test status
Simulation time 10700080488 ps
CPU time 1064.83 seconds
Started Mar 24 02:11:51 PM PDT 24
Finished Mar 24 02:29:36 PM PDT 24
Peak memory 317036 kb
Host smart-9102dd3a-39bc-44a0-bf6f-c2ccb11b7343
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128902138 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_an
d_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_long_msg_an
d_output.128902138 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/47.kmac_sideload.3412485518
Short name T604
Test name
Test status
Simulation time 4065118363 ps
CPU time 121.34 seconds
Started Mar 24 02:11:46 PM PDT 24
Finished Mar 24 02:13:48 PM PDT 24
Peak memory 234148 kb
Host smart-3e416263-6094-4e48-80c4-62f655a0b551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412485518 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload.3412485518 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_sideload/latest

Test location /workspace/coverage/default/47.kmac_smoke.3146296819
Short name T330
Test name
Test status
Simulation time 113885801 ps
CPU time 1.28 seconds
Started Mar 24 02:11:44 PM PDT 24
Finished Mar 24 02:11:45 PM PDT 24
Peak memory 224952 kb
Host smart-cffdba12-8624-4c1a-a61c-73a6a615ac9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146296819 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_smoke.3146296819 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_smoke/latest

Test location /workspace/coverage/default/47.kmac_stress_all.3044098994
Short name T701
Test name
Test status
Simulation time 17392962840 ps
CPU time 559.81 seconds
Started Mar 24 02:12:18 PM PDT 24
Finished Mar 24 02:21:38 PM PDT 24
Peak memory 264960 kb
Host smart-81590bbf-8398-4ef9-b6b3-f46e980fde89
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3044098994 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_stress_all.3044098994 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_stress_all/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac.134951285
Short name T274
Test name
Test status
Simulation time 241583643 ps
CPU time 6.34 seconds
Started Mar 24 02:12:02 PM PDT 24
Finished Mar 24 02:12:10 PM PDT 24
Peak memory 226764 kb
Host smart-61147aca-a231-49c8-912f-6843c434f44c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134951285 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 47.kmac_test_vectors_kmac.134951285 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_kmac_xof.3752916422
Short name T1048
Test name
Test status
Simulation time 608728452 ps
CPU time 6.98 seconds
Started Mar 24 02:12:04 PM PDT 24
Finished Mar 24 02:12:11 PM PDT 24
Peak memory 218704 kb
Host smart-931f7d8d-9000-42c8-99e3-f0aa6958eadc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752916422 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 47.kmac_test_vectors_kmac_xof.3752916422 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_224.3036201877
Short name T278
Test name
Test status
Simulation time 20244187428 ps
CPU time 2029.61 seconds
Started Mar 24 02:11:53 PM PDT 24
Finished Mar 24 02:45:43 PM PDT 24
Peak memory 397244 kb
Host smart-480ab61c-01e5-4ff8-ae22-de0fabafc0da
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3036201877 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_224.3036201877 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_256.1354785818
Short name T562
Test name
Test status
Simulation time 79728488418 ps
CPU time 1940.73 seconds
Started Mar 24 02:11:54 PM PDT 24
Finished Mar 24 02:44:15 PM PDT 24
Peak memory 386448 kb
Host smart-b1b519a5-d91f-4dc0-8f48-8394c194a24c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1354785818 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_256.1354785818 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_384.3659038547
Short name T920
Test name
Test status
Simulation time 125564559762 ps
CPU time 1643.29 seconds
Started Mar 24 02:11:59 PM PDT 24
Finished Mar 24 02:39:23 PM PDT 24
Peak memory 340532 kb
Host smart-6bd2a8cd-42d2-4cc0-b140-980ed9703f92
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3659038547 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_384.3659038547 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_sha3_512.983323530
Short name T380
Test name
Test status
Simulation time 171271321706 ps
CPU time 1290.79 seconds
Started Mar 24 02:11:57 PM PDT 24
Finished Mar 24 02:33:29 PM PDT 24
Peak memory 300732 kb
Host smart-0bf37b18-950b-440b-ab1f-1b602ff889fc
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=983323530 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_sha3_512.983323530 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_128.168036776
Short name T645
Test name
Test status
Simulation time 707298919870 ps
CPU time 6017.61 seconds
Started Mar 24 02:11:59 PM PDT 24
Finished Mar 24 03:52:18 PM PDT 24
Peak memory 657488 kb
Host smart-408cbf48-72eb-4348-b229-6e713c3e8f47
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=168036776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_128.168036776 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/47.kmac_test_vectors_shake_256.7180874
Short name T144
Test name
Test status
Simulation time 251899510057 ps
CPU time 4406.13 seconds
Started Mar 24 02:11:58 PM PDT 24
Finished Mar 24 03:25:25 PM PDT 24
Peak memory 577168 kb
Host smart-50e7742c-95e9-4a8c-8cc1-01d62ab1bb43
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=7180874 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_test_vectors_shake_256.7180874 +enable_masking=1 +sw_key_masked=0
Directory /workspace/47.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/48.kmac_alert_test.223407035
Short name T1081
Test name
Test status
Simulation time 17227947 ps
CPU time 0.83 seconds
Started Mar 24 02:12:47 PM PDT 24
Finished Mar 24 02:12:48 PM PDT 24
Peak memory 218484 kb
Host smart-78af9e07-a124-48dc-a2f3-6b64ed0b290e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223407035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_alert_test.223407035 +enable_m
asking=1 +sw_key_masked=0
Directory /workspace/48.kmac_alert_test/latest

Test location /workspace/coverage/default/48.kmac_app.1226277803
Short name T1057
Test name
Test status
Simulation time 4805800383 ps
CPU time 153.87 seconds
Started Mar 24 02:12:37 PM PDT 24
Finished Mar 24 02:15:11 PM PDT 24
Peak memory 243156 kb
Host smart-14b7e1cf-6cc4-48d6-87b2-0b0f0a65f294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226277803 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_app.1226277803 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_app/latest

Test location /workspace/coverage/default/48.kmac_burst_write.971041286
Short name T778
Test name
Test status
Simulation time 11497241040 ps
CPU time 289.84 seconds
Started Mar 24 02:12:23 PM PDT 24
Finished Mar 24 02:17:13 PM PDT 24
Peak memory 237924 kb
Host smart-4830be0c-c9ec-47f0-b30c-cee9bf615ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971041286 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_burst_write.971041286 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_burst_write/latest

Test location /workspace/coverage/default/48.kmac_entropy_refresh.1210864723
Short name T629
Test name
Test status
Simulation time 26855116276 ps
CPU time 180.36 seconds
Started Mar 24 02:12:38 PM PDT 24
Finished Mar 24 02:15:38 PM PDT 24
Peak memory 239160 kb
Host smart-2b036153-18a0-47e3-8762-ab048539daf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210864723 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_entropy_refresh.1210864723 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/48.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/48.kmac_error.1809359864
Short name T862
Test name
Test status
Simulation time 4365095167 ps
CPU time 100.35 seconds
Started Mar 24 02:12:37 PM PDT 24
Finished Mar 24 02:14:17 PM PDT 24
Peak memory 243208 kb
Host smart-afbd7a9b-af3f-491e-8241-34cee6151866
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809359864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_error.1809359864 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_error/latest

Test location /workspace/coverage/default/48.kmac_key_error.1323394270
Short name T884
Test name
Test status
Simulation time 73703150 ps
CPU time 1.25 seconds
Started Mar 24 02:12:44 PM PDT 24
Finished Mar 24 02:12:45 PM PDT 24
Peak memory 218552 kb
Host smart-46bd7429-a5d8-4e8b-806f-e4dd1ac8f1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323394270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_key_error.1323394270 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_key_error/latest

Test location /workspace/coverage/default/48.kmac_lc_escalation.3270936469
Short name T752
Test name
Test status
Simulation time 309346781 ps
CPU time 7.59 seconds
Started Mar 24 02:12:46 PM PDT 24
Finished Mar 24 02:12:53 PM PDT 24
Peak memory 227064 kb
Host smart-e8bf2230-e542-452d-919f-8c4618c8dc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270936469 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.3270936469 +enable_masking=1 +sw_k
ey_masked=0
Directory /workspace/48.kmac_lc_escalation/latest

Test location /workspace/coverage/default/48.kmac_long_msg_and_output.3319573213
Short name T960
Test name
Test status
Simulation time 3739622996 ps
CPU time 134.51 seconds
Started Mar 24 02:12:17 PM PDT 24
Finished Mar 24 02:14:32 PM PDT 24
Peak memory 238732 kb
Host smart-5e080522-1d8d-4b18-806f-1d8f276bcad0
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319573213 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_long_msg_a
nd_output.3319573213 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/48.kmac_sideload.649399336
Short name T266
Test name
Test status
Simulation time 4980780902 ps
CPU time 99.04 seconds
Started Mar 24 02:12:20 PM PDT 24
Finished Mar 24 02:13:59 PM PDT 24
Peak memory 232688 kb
Host smart-f5d440e4-5c76-41e0-a0d3-7c01cdc69bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649399336 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload.649399336 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_sideload/latest

Test location /workspace/coverage/default/48.kmac_smoke.198680153
Short name T864
Test name
Test status
Simulation time 208475179 ps
CPU time 7.01 seconds
Started Mar 24 02:12:19 PM PDT 24
Finished Mar 24 02:12:26 PM PDT 24
Peak memory 226700 kb
Host smart-c4caff4f-44a2-49fb-9dd1-b9d3a7bec440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198680153 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_smoke.198680153 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_smoke/latest

Test location /workspace/coverage/default/48.kmac_stress_all.1513887195
Short name T171
Test name
Test status
Simulation time 63623177209 ps
CPU time 1134.39 seconds
Started Mar 24 02:12:43 PM PDT 24
Finished Mar 24 02:31:38 PM PDT 24
Peak memory 344756 kb
Host smart-a766a882-265d-48cf-a936-a6f11f08952c
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1513887195 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_stress_all.1513887195 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_stress_all/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac.3052763041
Short name T674
Test name
Test status
Simulation time 264578660 ps
CPU time 6.26 seconds
Started Mar 24 02:12:35 PM PDT 24
Finished Mar 24 02:12:41 PM PDT 24
Peak memory 226720 kb
Host smart-1f197665-75f2-430f-9582-b2052ff3d054
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052763041 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 48.kmac_test_vectors_kmac.3052763041 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_kmac_xof.2728861005
Short name T933
Test name
Test status
Simulation time 543500812 ps
CPU time 6.68 seconds
Started Mar 24 02:12:39 PM PDT 24
Finished Mar 24 02:12:46 PM PDT 24
Peak memory 226668 kb
Host smart-5c326b8d-cc00-4a84-bb78-949e088ba936
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728861005 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 48.kmac_test_vectors_kmac_xof.2728861005 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_224.3011322585
Short name T195
Test name
Test status
Simulation time 68398641247 ps
CPU time 2132.04 seconds
Started Mar 24 02:12:21 PM PDT 24
Finished Mar 24 02:47:53 PM PDT 24
Peak memory 406040 kb
Host smart-9fe4f2ac-5927-4b65-a97d-f3eca9ab2ddf
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3011322585 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_224.3011322585 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_256.3905498870
Short name T480
Test name
Test status
Simulation time 94679727507 ps
CPU time 1762.92 seconds
Started Mar 24 02:12:21 PM PDT 24
Finished Mar 24 02:41:44 PM PDT 24
Peak memory 382056 kb
Host smart-30c7849e-3d79-4941-b697-e2d34e61cea1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3905498870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_256.3905498870 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_384.2443421045
Short name T32
Test name
Test status
Simulation time 40899749116 ps
CPU time 1570.59 seconds
Started Mar 24 02:12:21 PM PDT 24
Finished Mar 24 02:38:32 PM PDT 24
Peak memory 336988 kb
Host smart-bf53e27b-9671-462c-ac46-9577b8a5bd24
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2443421045 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_384.2443421045 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_sha3_512.1907212904
Short name T943
Test name
Test status
Simulation time 25853485521 ps
CPU time 1274.83 seconds
Started Mar 24 02:12:25 PM PDT 24
Finished Mar 24 02:33:40 PM PDT 24
Peak memory 300900 kb
Host smart-0852b41a-0966-4136-b910-c465b6bf0484
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1907212904 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_sha3_512.1907212904 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_128.102010810
Short name T464
Test name
Test status
Simulation time 259155587226 ps
CPU time 5061.48 seconds
Started Mar 24 02:12:31 PM PDT 24
Finished Mar 24 03:36:53 PM PDT 24
Peak memory 662856 kb
Host smart-70edf300-97b9-446d-b6eb-e9506aa44af0
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=102010810 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_128.102010810 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/48.kmac_test_vectors_shake_256.1332064054
Short name T404
Test name
Test status
Simulation time 313052486364 ps
CPU time 4954.92 seconds
Started Mar 24 02:12:30 PM PDT 24
Finished Mar 24 03:35:06 PM PDT 24
Peak memory 571380 kb
Host smart-51a39dbb-0fa7-4522-9066-ae5211e474ee
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1332064054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_test_vectors_shake_256.1332064054 +enable_masking=1 +sw_key_masked=0
Directory /workspace/48.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/49.kmac_alert_test.1712772597
Short name T183
Test name
Test status
Simulation time 59922395 ps
CPU time 0.83 seconds
Started Mar 24 02:13:21 PM PDT 24
Finished Mar 24 02:13:22 PM PDT 24
Peak memory 218440 kb
Host smart-52b3e07d-d28b-4099-81d2-2862413f92e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712772597 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_alert_test.1712772597 +enable
_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_alert_test/latest

Test location /workspace/coverage/default/49.kmac_app.1774003101
Short name T189
Test name
Test status
Simulation time 5549627404 ps
CPU time 66.5 seconds
Started Mar 24 02:13:05 PM PDT 24
Finished Mar 24 02:14:12 PM PDT 24
Peak memory 229500 kb
Host smart-129e6071-0082-4b1d-90ba-3bdd395a996f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774003101 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_app.1774003101 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_app/latest

Test location /workspace/coverage/default/49.kmac_burst_write.3249350206
Short name T149
Test name
Test status
Simulation time 80280786674 ps
CPU time 676.31 seconds
Started Mar 24 02:12:47 PM PDT 24
Finished Mar 24 02:24:04 PM PDT 24
Peak memory 234584 kb
Host smart-702fcab4-488b-424d-a9a7-9cc599500085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249350206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_burst_write.3249350206 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_burst_write/latest

Test location /workspace/coverage/default/49.kmac_entropy_refresh.3582247635
Short name T950
Test name
Test status
Simulation time 10506526468 ps
CPU time 250.64 seconds
Started Mar 24 02:13:07 PM PDT 24
Finished Mar 24 02:17:18 PM PDT 24
Peak memory 244376 kb
Host smart-afc837d3-9af2-4b10-a6c9-ea27566e5be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582247635 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_entropy_refresh.3582247635 +enable_masking=1 +
sw_key_masked=0
Directory /workspace/49.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/49.kmac_error.1593502807
Short name T59
Test name
Test status
Simulation time 39210978779 ps
CPU time 249.05 seconds
Started Mar 24 02:13:05 PM PDT 24
Finished Mar 24 02:17:14 PM PDT 24
Peak memory 252708 kb
Host smart-883031a4-0952-4fdc-891f-97259490ef3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593502807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_error.1593502807 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_error/latest

Test location /workspace/coverage/default/49.kmac_key_error.4185230870
Short name T17
Test name
Test status
Simulation time 10210253282 ps
CPU time 4.06 seconds
Started Mar 24 02:13:09 PM PDT 24
Finished Mar 24 02:13:13 PM PDT 24
Peak memory 218576 kb
Host smart-5e14d8e0-049a-4ece-8b11-a574f72cb66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185230870 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_key_error.4185230870 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_key_error/latest

Test location /workspace/coverage/default/49.kmac_lc_escalation.994946489
Short name T997
Test name
Test status
Simulation time 85995772 ps
CPU time 1.31 seconds
Started Mar 24 02:13:14 PM PDT 24
Finished Mar 24 02:13:16 PM PDT 24
Peak memory 218620 kb
Host smart-c3b839ec-9350-4b13-b975-9a4485af92e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994946489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.994946489 +enable_masking=1 +sw_key
_masked=0
Directory /workspace/49.kmac_lc_escalation/latest

Test location /workspace/coverage/default/49.kmac_long_msg_and_output.3510914070
Short name T374
Test name
Test status
Simulation time 26550641446 ps
CPU time 2453.65 seconds
Started Mar 24 02:12:47 PM PDT 24
Finished Mar 24 02:53:41 PM PDT 24
Peak memory 437896 kb
Host smart-64483476-e478-44e4-9604-4d4465701408
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510914070 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_long_msg_a
nd_output.3510914070 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/49.kmac_sideload.1531693061
Short name T527
Test name
Test status
Simulation time 55669337833 ps
CPU time 376.53 seconds
Started Mar 24 02:12:47 PM PDT 24
Finished Mar 24 02:19:04 PM PDT 24
Peak memory 248536 kb
Host smart-a8b1338b-347f-42f4-92ae-230f37666405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531693061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload.1531693061 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_sideload/latest

Test location /workspace/coverage/default/49.kmac_smoke.1146163130
Short name T314
Test name
Test status
Simulation time 29611858519 ps
CPU time 82.94 seconds
Started Mar 24 02:12:46 PM PDT 24
Finished Mar 24 02:14:09 PM PDT 24
Peak memory 226812 kb
Host smart-907344b6-75da-4694-94d9-a69836b2cd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146163130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_smoke.1146163130 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_smoke/latest

Test location /workspace/coverage/default/49.kmac_stress_all.2988478176
Short name T395
Test name
Test status
Simulation time 2992336340 ps
CPU time 38.91 seconds
Started Mar 24 02:13:16 PM PDT 24
Finished Mar 24 02:13:55 PM PDT 24
Peak memory 234932 kb
Host smart-bbcb19d0-b9b2-472c-9c06-fd1b42937158
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2988478176 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_stress_all.2988478176 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_stress_all/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac.3864149625
Short name T550
Test name
Test status
Simulation time 264638143 ps
CPU time 6.23 seconds
Started Mar 24 02:13:01 PM PDT 24
Finished Mar 24 02:13:08 PM PDT 24
Peak memory 218708 kb
Host smart-aa52c09a-9269-494f-84b7-ca9351c06a4f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864149625 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 49.kmac_test_vectors_kmac.3864149625 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_kmac_xof.2904310596
Short name T937
Test name
Test status
Simulation time 260373290 ps
CPU time 6.24 seconds
Started Mar 24 02:13:01 PM PDT 24
Finished Mar 24 02:13:08 PM PDT 24
Peak memory 218548 kb
Host smart-c5f47cc5-c23b-4940-aa47-21cd79a2ab99
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904310596 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 49.kmac_test_vectors_kmac_xof.2904310596 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_224.1238917313
Short name T397
Test name
Test status
Simulation time 118625211318 ps
CPU time 1987.35 seconds
Started Mar 24 02:12:47 PM PDT 24
Finished Mar 24 02:45:54 PM PDT 24
Peak memory 391892 kb
Host smart-42d26cae-b334-498e-858e-da1793d161c1
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1238917313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_224.1238917313 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_256.2477914709
Short name T941
Test name
Test status
Simulation time 64248228546 ps
CPU time 2150.04 seconds
Started Mar 24 02:12:51 PM PDT 24
Finished Mar 24 02:48:41 PM PDT 24
Peak memory 388952 kb
Host smart-ba003df3-4053-48a6-8029-ba987448668a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2477914709 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_256.2477914709 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_384.1118358807
Short name T209
Test name
Test status
Simulation time 192881554419 ps
CPU time 1762.55 seconds
Started Mar 24 02:12:51 PM PDT 24
Finished Mar 24 02:42:14 PM PDT 24
Peak memory 334980 kb
Host smart-432531d7-ed0e-4eae-bab3-d9df3ed94197
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1118358807 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_384.1118358807 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_sha3_512.4072378465
Short name T844
Test name
Test status
Simulation time 142433243377 ps
CPU time 1243.97 seconds
Started Mar 24 02:12:52 PM PDT 24
Finished Mar 24 02:33:36 PM PDT 24
Peak memory 302840 kb
Host smart-747eb844-10f0-4b4f-87da-cf91bccb03f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4072378465 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_sha3_512.4072378465 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_128.2500362450
Short name T199
Test name
Test status
Simulation time 1061110390175 ps
CPU time 5318.07 seconds
Started Mar 24 02:12:55 PM PDT 24
Finished Mar 24 03:41:34 PM PDT 24
Peak memory 652772 kb
Host smart-a4fde9b4-b981-4291-aee3-bfc5b75bbb53
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2500362450 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_128.2500362450 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/49.kmac_test_vectors_shake_256.1210841525
Short name T355
Test name
Test status
Simulation time 54920649311 ps
CPU time 4243.16 seconds
Started Mar 24 02:12:56 PM PDT 24
Finished Mar 24 03:23:40 PM PDT 24
Peak memory 567296 kb
Host smart-241e9e35-e16f-4e6f-8e9b-4c6ad3c5deea
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1210841525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_test_vectors_shake_256.1210841525 +enable_masking=1 +sw_key_masked=0
Directory /workspace/49.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/5.kmac_alert_test.3187605595
Short name T697
Test name
Test status
Simulation time 29992890 ps
CPU time 0.86 seconds
Started Mar 24 01:58:00 PM PDT 24
Finished Mar 24 01:58:01 PM PDT 24
Peak memory 218504 kb
Host smart-c575d29b-edeb-4acf-8f06-b2c508f945f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187605595 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.3187605595 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_alert_test/latest

Test location /workspace/coverage/default/5.kmac_app.2498628720
Short name T912
Test name
Test status
Simulation time 6965202106 ps
CPU time 169.64 seconds
Started Mar 24 01:57:59 PM PDT 24
Finished Mar 24 02:00:49 PM PDT 24
Peak memory 240796 kb
Host smart-6334c5c3-7b50-4d1c-a588-d6a73f71ab76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498628720 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.2498628720 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app/latest

Test location /workspace/coverage/default/5.kmac_app_with_partial_data.1975806599
Short name T927
Test name
Test status
Simulation time 21992383335 ps
CPU time 385.27 seconds
Started Mar 24 01:58:02 PM PDT 24
Finished Mar 24 02:04:28 PM PDT 24
Peak memory 251180 kb
Host smart-4a2c54c6-209d-41c4-b017-c611cca8f3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975806599 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.1975806599 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/5.kmac_burst_write.2818040488
Short name T508
Test name
Test status
Simulation time 98556156881 ps
CPU time 1476.49 seconds
Started Mar 24 01:57:54 PM PDT 24
Finished Mar 24 02:22:31 PM PDT 24
Peak memory 241044 kb
Host smart-34829ec2-4a45-45e5-90ed-d73d16b380ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818040488 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.2818040488 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_burst_write/latest

Test location /workspace/coverage/default/5.kmac_edn_timeout_error.1814789837
Short name T147
Test name
Test status
Simulation time 240010148 ps
CPU time 1.27 seconds
Started Mar 24 01:58:03 PM PDT 24
Finished Mar 24 01:58:04 PM PDT 24
Peak memory 218568 kb
Host smart-8aad4628-f460-4680-8704-27d5b8ee07ad
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1814789837 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1814789837 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_mode_error.1753124014
Short name T698
Test name
Test status
Simulation time 32627329 ps
CPU time 1.15 seconds
Started Mar 24 01:58:01 PM PDT 24
Finished Mar 24 01:58:02 PM PDT 24
Peak memory 221836 kb
Host smart-57a775fc-c0a7-4bea-9e16-4998bcf3253c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1753124014 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.1753124014 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_ready_error.3433579678
Short name T788
Test name
Test status
Simulation time 26005666023 ps
CPU time 76.39 seconds
Started Mar 24 01:58:00 PM PDT 24
Finished Mar 24 01:59:17 PM PDT 24
Peak memory 226772 kb
Host smart-10e0f9da-0301-4f74-96c5-453891cd8a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433579678 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.3433579678 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/5.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/5.kmac_entropy_refresh.2773128797
Short name T803
Test name
Test status
Simulation time 14457368179 ps
CPU time 161.86 seconds
Started Mar 24 01:57:59 PM PDT 24
Finished Mar 24 02:00:41 PM PDT 24
Peak memory 238576 kb
Host smart-19d60e5d-5c2d-481c-a0a6-cda378f61fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773128797 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.2773128797 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/5.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/5.kmac_error.1295427650
Short name T751
Test name
Test status
Simulation time 24694253731 ps
CPU time 487.91 seconds
Started Mar 24 01:58:01 PM PDT 24
Finished Mar 24 02:06:10 PM PDT 24
Peak memory 275944 kb
Host smart-f7649a10-dec9-4cb2-8d80-cc2862c4d219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295427650 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.1295427650 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_error/latest

Test location /workspace/coverage/default/5.kmac_key_error.1161256893
Short name T349
Test name
Test status
Simulation time 1653741610 ps
CPU time 2.75 seconds
Started Mar 24 01:58:00 PM PDT 24
Finished Mar 24 01:58:03 PM PDT 24
Peak memory 218576 kb
Host smart-b7887e23-c587-4593-941c-60444315a2bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161256893 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.1161256893 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_key_error/latest

Test location /workspace/coverage/default/5.kmac_lc_escalation.814641375
Short name T956
Test name
Test status
Simulation time 70210459 ps
CPU time 1.21 seconds
Started Mar 24 01:58:03 PM PDT 24
Finished Mar 24 01:58:04 PM PDT 24
Peak memory 218548 kb
Host smart-491a9e0d-d551-4396-95a9-d839ce02e300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814641375 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.814641375 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_lc_escalation/latest

Test location /workspace/coverage/default/5.kmac_long_msg_and_output.3667424584
Short name T568
Test name
Test status
Simulation time 5553924588 ps
CPU time 148.58 seconds
Started Mar 24 01:58:00 PM PDT 24
Finished Mar 24 02:00:28 PM PDT 24
Peak memory 242644 kb
Host smart-1d4cb92a-acc1-49a4-9c74-60b42e5893c4
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667424584 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_an
d_output.3667424584 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/5.kmac_mubi.4136678093
Short name T581
Test name
Test status
Simulation time 12006628409 ps
CPU time 257.73 seconds
Started Mar 24 01:57:58 PM PDT 24
Finished Mar 24 02:02:16 PM PDT 24
Peak memory 245792 kb
Host smart-ff95d0aa-d50b-4b5c-8c3c-d472caf12740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4136678093 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.4136678093 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_mubi/latest

Test location /workspace/coverage/default/5.kmac_sideload.2584568315
Short name T256
Test name
Test status
Simulation time 11198192139 ps
CPU time 379.79 seconds
Started Mar 24 01:57:54 PM PDT 24
Finished Mar 24 02:04:14 PM PDT 24
Peak memory 248612 kb
Host smart-9e2b0dea-1e77-4146-acb7-04b13bd99930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584568315 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.2584568315 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_sideload/latest

Test location /workspace/coverage/default/5.kmac_smoke.2228647785
Short name T298
Test name
Test status
Simulation time 3330160947 ps
CPU time 86.61 seconds
Started Mar 24 01:57:54 PM PDT 24
Finished Mar 24 01:59:20 PM PDT 24
Peak memory 226700 kb
Host smart-b95d1ffc-a05d-47f7-893f-c71cd5445d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228647785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.2228647785 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_smoke/latest

Test location /workspace/coverage/default/5.kmac_stress_all.4255675919
Short name T662
Test name
Test status
Simulation time 51517580477 ps
CPU time 713.6 seconds
Started Mar 24 01:58:03 PM PDT 24
Finished Mar 24 02:09:57 PM PDT 24
Peak memory 297420 kb
Host smart-a4e22b8a-14e2-4fd8-9dcf-c7a260200f58
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=4255675919 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all.4255675919 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all/latest

Test location /workspace/coverage/default/5.kmac_stress_all_with_rand_reset.2806329942
Short name T118
Test name
Test status
Simulation time 39017325552 ps
CPU time 1132.86 seconds
Started Mar 24 01:58:00 PM PDT 24
Finished Mar 24 02:16:53 PM PDT 24
Peak memory 320516 kb
Host smart-ded89496-8c29-440d-9616-ba1f3acd089d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=1000000000
0 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2806329942 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_rand_reset.2806329942 +en
able_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac.128722134
Short name T781
Test name
Test status
Simulation time 1414740926 ps
CPU time 6.45 seconds
Started Mar 24 01:57:58 PM PDT 24
Finished Mar 24 01:58:05 PM PDT 24
Peak memory 226708 kb
Host smart-c0566c9e-be26-4bf4-9b7b-4b09295b91a9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128722134 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 5.kmac_test_vectors_kmac.128722134 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_kmac_xof.4245163359
Short name T622
Test name
Test status
Simulation time 838775071 ps
CPU time 6.2 seconds
Started Mar 24 01:58:02 PM PDT 24
Finished Mar 24 01:58:08 PM PDT 24
Peak memory 219652 kb
Host smart-00f20407-f641-4c58-b754-f8b183bf973e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245163359 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 5.kmac_test_vectors_kmac_xof.4245163359 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_224.3311715280
Short name T615
Test name
Test status
Simulation time 391275637130 ps
CPU time 2653.92 seconds
Started Mar 24 01:57:56 PM PDT 24
Finished Mar 24 02:42:10 PM PDT 24
Peak memory 399132 kb
Host smart-7e0f7efa-740a-40d4-aa50-b863e789039a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3311715280 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_224.3311715280 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_256.2119078137
Short name T714
Test name
Test status
Simulation time 98063214709 ps
CPU time 2363.83 seconds
Started Mar 24 01:57:55 PM PDT 24
Finished Mar 24 02:37:19 PM PDT 24
Peak memory 396360 kb
Host smart-f3158fbe-a924-44b4-b2fb-43270a2ce4e5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2119078137 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_256.2119078137 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_384.2388013916
Short name T742
Test name
Test status
Simulation time 164120222735 ps
CPU time 1536.72 seconds
Started Mar 24 01:57:56 PM PDT 24
Finished Mar 24 02:23:33 PM PDT 24
Peak memory 340500 kb
Host smart-f891f9f6-0698-4610-9b3e-4b82b720b878
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2388013916 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_384.2388013916 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_sha3_512.4219396764
Short name T823
Test name
Test status
Simulation time 49478964206 ps
CPU time 1274 seconds
Started Mar 24 01:57:57 PM PDT 24
Finished Mar 24 02:19:11 PM PDT 24
Peak memory 295600 kb
Host smart-f3823233-63d4-441d-a786-f53fe981990a
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4219396764 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_sha3_512.4219396764 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_128.3219658953
Short name T512
Test name
Test status
Simulation time 1695531313168 ps
CPU time 6023.97 seconds
Started Mar 24 01:57:55 PM PDT 24
Finished Mar 24 03:38:20 PM PDT 24
Peak memory 629804 kb
Host smart-1bf713b3-f873-4997-aada-ca3fe28d88df
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3219658953 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_128.3219658953 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/5.kmac_test_vectors_shake_256.953645520
Short name T493
Test name
Test status
Simulation time 1711563853839 ps
CPU time 5912.98 seconds
Started Mar 24 01:58:01 PM PDT 24
Finished Mar 24 03:36:35 PM PDT 24
Peak memory 583436 kb
Host smart-5158909c-ea0c-418c-8dab-5f60662bf120
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=953645520 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_test_vectors_shake_256.953645520 +enable_masking=1 +sw_key_masked=0
Directory /workspace/5.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/6.kmac_alert_test.1828103649
Short name T244
Test name
Test status
Simulation time 15366618 ps
CPU time 0.82 seconds
Started Mar 24 01:58:04 PM PDT 24
Finished Mar 24 01:58:05 PM PDT 24
Peak memory 218484 kb
Host smart-8c6eda41-78d6-4db0-9df1-f6d061c7bbab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1828103649 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.1828103649 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_alert_test/latest

Test location /workspace/coverage/default/6.kmac_app.429633971
Short name T408
Test name
Test status
Simulation time 1378910040 ps
CPU time 17.22 seconds
Started Mar 24 01:58:05 PM PDT 24
Finished Mar 24 01:58:22 PM PDT 24
Peak memory 227612 kb
Host smart-0fb27ad8-d838-4177-9c9a-a6cf6247120a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429633971 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.429633971 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app/latest

Test location /workspace/coverage/default/6.kmac_app_with_partial_data.1816358515
Short name T716
Test name
Test status
Simulation time 39775041026 ps
CPU time 223.58 seconds
Started Mar 24 01:58:04 PM PDT 24
Finished Mar 24 02:01:48 PM PDT 24
Peak memory 242256 kb
Host smart-d894bf04-f225-4b91-af7f-2a2d27e4af2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816358515 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.1816358515 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/6.kmac_edn_timeout_error.2891587646
Short name T301
Test name
Test status
Simulation time 45843795 ps
CPU time 1.22 seconds
Started Mar 24 01:58:03 PM PDT 24
Finished Mar 24 01:58:04 PM PDT 24
Peak memory 218628 kb
Host smart-8a2bf9ce-7973-490d-a3cc-d3d7b7764592
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2891587646 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.2891587646 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_mode_error.890123146
Short name T996
Test name
Test status
Simulation time 2015484119 ps
CPU time 48.57 seconds
Started Mar 24 01:58:05 PM PDT 24
Finished Mar 24 01:58:54 PM PDT 24
Peak memory 227644 kb
Host smart-143a4420-de70-4ebc-93fe-4174592ca7ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=890123146 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.890123146 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_ready_error.665685099
Short name T728
Test name
Test status
Simulation time 9283714694 ps
CPU time 25.69 seconds
Started Mar 24 01:58:05 PM PDT 24
Finished Mar 24 01:58:31 PM PDT 24
Peak memory 226776 kb
Host smart-00ccdb00-2156-460b-8470-1ed788f11599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665685099 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.665685099 +enable_maskin
g=1 +sw_key_masked=0
Directory /workspace/6.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/6.kmac_entropy_refresh.3154365454
Short name T507
Test name
Test status
Simulation time 8843244871 ps
CPU time 352.45 seconds
Started Mar 24 01:58:04 PM PDT 24
Finished Mar 24 02:03:57 PM PDT 24
Peak memory 248164 kb
Host smart-206c9e1e-2b88-474d-a0d5-2b2765f9a892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154365454 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.3154365454 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/6.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/6.kmac_error.472728882
Short name T285
Test name
Test status
Simulation time 3157216121 ps
CPU time 96.93 seconds
Started Mar 24 01:58:05 PM PDT 24
Finished Mar 24 01:59:42 PM PDT 24
Peak memory 243172 kb
Host smart-915151f8-9055-4ca0-8fc7-bf2a1eae19ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472728882 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.472728882 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_error/latest

Test location /workspace/coverage/default/6.kmac_key_error.1666724525
Short name T989
Test name
Test status
Simulation time 400218458 ps
CPU time 2.71 seconds
Started Mar 24 01:58:06 PM PDT 24
Finished Mar 24 01:58:09 PM PDT 24
Peak memory 218732 kb
Host smart-f31ccbbb-64fc-49e2-8981-1c66d5c4128f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666724525 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.1666724525 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_key_error/latest

Test location /workspace/coverage/default/6.kmac_lc_escalation.2562794265
Short name T891
Test name
Test status
Simulation time 51387604 ps
CPU time 1.42 seconds
Started Mar 24 01:58:05 PM PDT 24
Finished Mar 24 01:58:07 PM PDT 24
Peak memory 218592 kb
Host smart-e0f47fa5-4576-4486-8ee6-0ec5b092391c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562794265 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.2562794265 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/6.kmac_lc_escalation/latest

Test location /workspace/coverage/default/6.kmac_long_msg_and_output.2718905861
Short name T893
Test name
Test status
Simulation time 140595174007 ps
CPU time 1470.44 seconds
Started Mar 24 01:58:03 PM PDT 24
Finished Mar 24 02:22:34 PM PDT 24
Peak memory 343460 kb
Host smart-102bd13c-131f-4391-a147-ed1f8bb86c39
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718905861 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_an
d_output.2718905861 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/6.kmac_mubi.1658733489
Short name T994
Test name
Test status
Simulation time 8705399786 ps
CPU time 133 seconds
Started Mar 24 01:58:05 PM PDT 24
Finished Mar 24 02:00:18 PM PDT 24
Peak memory 236012 kb
Host smart-ff6b0661-d370-4270-be0b-6b28984a4f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658733489 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.1658733489 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_mubi/latest

Test location /workspace/coverage/default/6.kmac_sideload.3107784358
Short name T840
Test name
Test status
Simulation time 2618631950 ps
CPU time 47.93 seconds
Started Mar 24 01:58:02 PM PDT 24
Finished Mar 24 01:58:50 PM PDT 24
Peak memory 227792 kb
Host smart-c90ad906-caf6-4852-96bc-17eb47c94045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107784358 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.3107784358 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_sideload/latest

Test location /workspace/coverage/default/6.kmac_smoke.1259924262
Short name T204
Test name
Test status
Simulation time 623955645 ps
CPU time 11.12 seconds
Started Mar 24 01:58:01 PM PDT 24
Finished Mar 24 01:58:12 PM PDT 24
Peak memory 226676 kb
Host smart-1d00dff4-7f62-4ea2-ad29-93ab1de635e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259924262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.1259924262 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_smoke/latest

Test location /workspace/coverage/default/6.kmac_stress_all.251620805
Short name T838
Test name
Test status
Simulation time 252282875395 ps
CPU time 495.89 seconds
Started Mar 24 01:58:05 PM PDT 24
Finished Mar 24 02:06:21 PM PDT 24
Peak memory 274392 kb
Host smart-229953f5-e044-4b0d-a491-cf09a48394e8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=251620805 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all.251620805 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_stress_all/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac.3996092297
Short name T1034
Test name
Test status
Simulation time 201566464 ps
CPU time 6.66 seconds
Started Mar 24 01:58:03 PM PDT 24
Finished Mar 24 01:58:09 PM PDT 24
Peak memory 226776 kb
Host smart-0e770b01-159f-4f11-9397-e24c885264d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996092297 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 6.kmac_test_vectors_kmac.3996092297 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_kmac_xof.639670118
Short name T1016
Test name
Test status
Simulation time 820555487 ps
CPU time 6.1 seconds
Started Mar 24 01:58:06 PM PDT 24
Finished Mar 24 01:58:12 PM PDT 24
Peak memory 218696 kb
Host smart-37719847-5732-4bee-a317-0e2f6060cd29
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639670118 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /
dev/null -cm_name 6.kmac_test_vectors_kmac_xof.639670118 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_224.1216076086
Short name T496
Test name
Test status
Simulation time 102948675220 ps
CPU time 2397.79 seconds
Started Mar 24 01:58:04 PM PDT 24
Finished Mar 24 02:38:02 PM PDT 24
Peak memory 405024 kb
Host smart-c25bf611-9abc-4c8b-9419-beb135d20e48
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1216076086 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_224.1216076086 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_256.2964045410
Short name T1055
Test name
Test status
Simulation time 19596991755 ps
CPU time 2054.68 seconds
Started Mar 24 01:58:06 PM PDT 24
Finished Mar 24 02:32:21 PM PDT 24
Peak memory 395272 kb
Host smart-c5903d34-eea2-4961-abf4-60ffe8da6cc7
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2964045410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_256.2964045410 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_384.723409822
Short name T596
Test name
Test status
Simulation time 648052800938 ps
CPU time 1730.63 seconds
Started Mar 24 01:58:05 PM PDT 24
Finished Mar 24 02:26:56 PM PDT 24
Peak memory 342440 kb
Host smart-106dd8b4-6a39-451e-9c49-5c56b2ba73d9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=723409822 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_384.723409822 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_sha3_512.987820168
Short name T702
Test name
Test status
Simulation time 50607377425 ps
CPU time 1249.67 seconds
Started Mar 24 01:58:06 PM PDT 24
Finished Mar 24 02:18:56 PM PDT 24
Peak memory 296392 kb
Host smart-bd186bea-d8c9-43e8-9830-c014aed2d95d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=987820168 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_sha3_512.987820168 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_128.955114922
Short name T583
Test name
Test status
Simulation time 743532677812 ps
CPU time 6138.7 seconds
Started Mar 24 01:58:05 PM PDT 24
Finished Mar 24 03:40:25 PM PDT 24
Peak memory 660788 kb
Host smart-9208d64c-89ad-4186-874a-e45746a57cc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=955114922 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_128.955114922 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/6.kmac_test_vectors_shake_256.2431007232
Short name T405
Test name
Test status
Simulation time 52184540296 ps
CPU time 4550.59 seconds
Started Mar 24 01:58:05 PM PDT 24
Finished Mar 24 03:13:56 PM PDT 24
Peak memory 570432 kb
Host smart-7a6d7133-2f70-447e-886e-eef06abaf81b
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=2431007232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_test_vectors_shake_256.2431007232 +enable_masking=1 +sw_key_masked=0
Directory /workspace/6.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/7.kmac_alert_test.178719156
Short name T478
Test name
Test status
Simulation time 35130979 ps
CPU time 0.92 seconds
Started Mar 24 01:58:14 PM PDT 24
Finished Mar 24 01:58:15 PM PDT 24
Peak memory 218460 kb
Host smart-2da4f77d-32d9-41d2-b608-85bf2099cf9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178719156 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.178719156 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/7.kmac_alert_test/latest

Test location /workspace/coverage/default/7.kmac_app.1853959776
Short name T847
Test name
Test status
Simulation time 2471500572 ps
CPU time 138.33 seconds
Started Mar 24 01:58:10 PM PDT 24
Finished Mar 24 02:00:28 PM PDT 24
Peak memory 243120 kb
Host smart-666b6d4a-09a1-4f1c-a1da-140e141df9d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853959776 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.1853959776 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_app/latest

Test location /workspace/coverage/default/7.kmac_burst_write.3014825313
Short name T1053
Test name
Test status
Simulation time 26090320453 ps
CPU time 1259.27 seconds
Started Mar 24 01:58:10 PM PDT 24
Finished Mar 24 02:19:09 PM PDT 24
Peak memory 243188 kb
Host smart-10b084a0-329b-4fb9-a7c5-7f6c358d36ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014825313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.3014825313 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_burst_write/latest

Test location /workspace/coverage/default/7.kmac_edn_timeout_error.1819997771
Short name T286
Test name
Test status
Simulation time 350483846 ps
CPU time 12.7 seconds
Started Mar 24 01:58:22 PM PDT 24
Finished Mar 24 01:58:35 PM PDT 24
Peak memory 236972 kb
Host smart-31ed3621-e5d1-471b-b102-360077976639
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1819997771 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.1819997771 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_mode_error.4250877328
Short name T588
Test name
Test status
Simulation time 6729923368 ps
CPU time 41.37 seconds
Started Mar 24 01:58:16 PM PDT 24
Finished Mar 24 01:58:58 PM PDT 24
Peak memory 234948 kb
Host smart-109c981c-6ceb-464e-bd75-abcdd968975b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4250877328 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.4250877328 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_ready_error.3476795408
Short name T881
Test name
Test status
Simulation time 5055658384 ps
CPU time 49.02 seconds
Started Mar 24 01:58:22 PM PDT 24
Finished Mar 24 01:59:11 PM PDT 24
Peak memory 226592 kb
Host smart-6ad7007c-0112-4b13-8775-02647efb08f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476795408 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.3476795408 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/7.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/7.kmac_entropy_refresh.2966927841
Short name T495
Test name
Test status
Simulation time 6677375801 ps
CPU time 80.34 seconds
Started Mar 24 01:58:15 PM PDT 24
Finished Mar 24 01:59:35 PM PDT 24
Peak memory 232552 kb
Host smart-af462504-97d1-4b67-9052-6a6085823da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966927841 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.2966927841 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/7.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/7.kmac_error.977825774
Short name T644
Test name
Test status
Simulation time 1370445136 ps
CPU time 66.98 seconds
Started Mar 24 01:58:22 PM PDT 24
Finished Mar 24 01:59:29 PM PDT 24
Peak memory 243100 kb
Host smart-55a53148-66f1-4293-8021-f96f0a5e12ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977825774 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.977825774 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_error/latest

Test location /workspace/coverage/default/7.kmac_key_error.208890636
Short name T1014
Test name
Test status
Simulation time 1410067999 ps
CPU time 2.97 seconds
Started Mar 24 01:58:15 PM PDT 24
Finished Mar 24 01:58:18 PM PDT 24
Peak memory 218540 kb
Host smart-12bed765-20ed-49c1-b99e-42c640ff6bca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208890636 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.208890636 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_key_error/latest

Test location /workspace/coverage/default/7.kmac_lc_escalation.290763451
Short name T23
Test name
Test status
Simulation time 87002223 ps
CPU time 1.6 seconds
Started Mar 24 01:58:13 PM PDT 24
Finished Mar 24 01:58:15 PM PDT 24
Peak memory 219536 kb
Host smart-e6fdc80d-7205-4e0d-a7f8-0817fc5e8691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290763451 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.290763451 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_lc_escalation/latest

Test location /workspace/coverage/default/7.kmac_long_msg_and_output.3695575701
Short name T105
Test name
Test status
Simulation time 321437350735 ps
CPU time 679.83 seconds
Started Mar 24 01:58:09 PM PDT 24
Finished Mar 24 02:09:29 PM PDT 24
Peak memory 277112 kb
Host smart-0e753ff6-2666-4490-bbe4-784f2747ca75
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695575701 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_an
d_output.3695575701 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/7.kmac_mubi.3091197713
Short name T431
Test name
Test status
Simulation time 7789728002 ps
CPU time 45.38 seconds
Started Mar 24 01:58:17 PM PDT 24
Finished Mar 24 01:59:03 PM PDT 24
Peak memory 227672 kb
Host smart-7a78f821-b778-4b3b-8ef2-f16d95d0b7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091197713 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.3091197713 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_mubi/latest

Test location /workspace/coverage/default/7.kmac_sideload.2360717545
Short name T1069
Test name
Test status
Simulation time 2057786493 ps
CPU time 48.11 seconds
Started Mar 24 01:58:13 PM PDT 24
Finished Mar 24 01:59:01 PM PDT 24
Peak memory 225100 kb
Host smart-01df8852-524f-47c3-a44a-02391d27754e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360717545 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.2360717545 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_sideload/latest

Test location /workspace/coverage/default/7.kmac_smoke.3075446880
Short name T783
Test name
Test status
Simulation time 346679869 ps
CPU time 4.64 seconds
Started Mar 24 01:58:11 PM PDT 24
Finished Mar 24 01:58:15 PM PDT 24
Peak memory 219536 kb
Host smart-3ca3d3c5-3da6-4fe8-8d28-84dddfbcb087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075446880 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.3075446880 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_smoke/latest

Test location /workspace/coverage/default/7.kmac_stress_all.1452378425
Short name T249
Test name
Test status
Simulation time 2514211380 ps
CPU time 60.84 seconds
Started Mar 24 01:58:14 PM PDT 24
Finished Mar 24 01:59:15 PM PDT 24
Peak memory 230552 kb
Host smart-675ff70d-6274-4007-8aa2-223e6d49d643
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=1452378425 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all.1452378425 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_stress_all/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac.2473012047
Short name T671
Test name
Test status
Simulation time 272156910 ps
CPU time 6.47 seconds
Started Mar 24 01:58:11 PM PDT 24
Finished Mar 24 01:58:17 PM PDT 24
Peak memory 218700 kb
Host smart-32407b1f-d448-4b9a-bb6f-b8bae1d267f2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473012047 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 7.kmac_test_vectors_kmac.2473012047 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_kmac_xof.1251181209
Short name T420
Test name
Test status
Simulation time 433995792 ps
CPU time 6.83 seconds
Started Mar 24 01:58:13 PM PDT 24
Finished Mar 24 01:58:20 PM PDT 24
Peak memory 218644 kb
Host smart-53958c4c-e7cc-4180-bd19-b62e0b5b4c63
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251181209 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 7.kmac_test_vectors_kmac_xof.1251181209 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_224.1316190103
Short name T432
Test name
Test status
Simulation time 337480753246 ps
CPU time 2050.73 seconds
Started Mar 24 01:58:11 PM PDT 24
Finished Mar 24 02:32:22 PM PDT 24
Peak memory 388732 kb
Host smart-70ce3b60-599b-4d55-bea7-e3a6a0d42fce
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1316190103 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_224.1316190103 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_256.2225241632
Short name T600
Test name
Test status
Simulation time 38779613563 ps
CPU time 1828.21 seconds
Started Mar 24 01:58:13 PM PDT 24
Finished Mar 24 02:28:42 PM PDT 24
Peak memory 388276 kb
Host smart-444fd86a-6574-4ed3-a0b6-c0bf20c1d08f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2225241632 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_256.2225241632 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_384.2415376365
Short name T855
Test name
Test status
Simulation time 53327176528 ps
CPU time 1566.99 seconds
Started Mar 24 01:58:12 PM PDT 24
Finished Mar 24 02:24:19 PM PDT 24
Peak memory 341380 kb
Host smart-b074d82b-a83b-41cd-b4fc-1dcc8d7eb2eb
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2415376365 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_384.2415376365 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_sha3_512.3186394262
Short name T799
Test name
Test status
Simulation time 22044489192 ps
CPU time 1211.97 seconds
Started Mar 24 01:58:11 PM PDT 24
Finished Mar 24 02:18:24 PM PDT 24
Peak memory 306148 kb
Host smart-43deb395-42e5-473e-9408-79fcb8d6bb0e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3186394262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_sha3_512.3186394262 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_128.3752856438
Short name T148
Test name
Test status
Simulation time 186779146749 ps
CPU time 5988.57 seconds
Started Mar 24 01:58:12 PM PDT 24
Finished Mar 24 03:38:01 PM PDT 24
Peak memory 658752 kb
Host smart-9eb5f9ea-d45a-4671-9c4d-c88708a00c94
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3752856438 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_128.3752856438 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/7.kmac_test_vectors_shake_256.545016785
Short name T1051
Test name
Test status
Simulation time 218507485425 ps
CPU time 4343.69 seconds
Started Mar 24 01:58:12 PM PDT 24
Finished Mar 24 03:10:36 PM PDT 24
Peak memory 567884 kb
Host smart-ac316771-5689-43bc-a924-763ca3a4761c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=545016785 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_test_vectors_shake_256.545016785 +enable_masking=1 +sw_key_masked=0
Directory /workspace/7.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/8.kmac_alert_test.673696054
Short name T331
Test name
Test status
Simulation time 17470014 ps
CPU time 0.83 seconds
Started Mar 24 01:58:24 PM PDT 24
Finished Mar 24 01:58:25 PM PDT 24
Peak memory 220492 kb
Host smart-cbbabe96-92ed-4220-8c2a-0a9020c4f00e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673696054 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.673696054 +enable_ma
sking=1 +sw_key_masked=0
Directory /workspace/8.kmac_alert_test/latest

Test location /workspace/coverage/default/8.kmac_app.4140133061
Short name T797
Test name
Test status
Simulation time 10547877472 ps
CPU time 212.59 seconds
Started Mar 24 01:58:22 PM PDT 24
Finished Mar 24 02:01:55 PM PDT 24
Peak memory 241192 kb
Host smart-ceb354aa-6b9c-4cec-8eb5-83b970126afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140133061 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.4140133061 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app/latest

Test location /workspace/coverage/default/8.kmac_app_with_partial_data.3381321747
Short name T754
Test name
Test status
Simulation time 54522615111 ps
CPU time 357.74 seconds
Started Mar 24 01:58:15 PM PDT 24
Finished Mar 24 02:04:13 PM PDT 24
Peak memory 251736 kb
Host smart-45d74624-f2eb-4a5c-8e45-9ec92f928b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381321747 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.3381321747 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/8.kmac_burst_write.2268995270
Short name T720
Test name
Test status
Simulation time 8676708385 ps
CPU time 931.37 seconds
Started Mar 24 01:58:16 PM PDT 24
Finished Mar 24 02:13:48 PM PDT 24
Peak memory 235056 kb
Host smart-24eef777-ce02-4755-a5b8-dbb6d5706ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268995270 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.2268995270 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_burst_write/latest

Test location /workspace/coverage/default/8.kmac_edn_timeout_error.2259359641
Short name T65
Test name
Test status
Simulation time 45062355 ps
CPU time 0.87 seconds
Started Mar 24 01:58:20 PM PDT 24
Finished Mar 24 01:58:21 PM PDT 24
Peak memory 218484 kb
Host smart-2c340115-7353-4f6b-9c45-7349a351deb1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2259359641 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.2259359641 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_mode_error.267635196
Short name T683
Test name
Test status
Simulation time 59012382 ps
CPU time 0.88 seconds
Started Mar 24 01:58:19 PM PDT 24
Finished Mar 24 01:58:20 PM PDT 24
Peak memory 220576 kb
Host smart-773fa25e-575d-4f4f-8082-2776e2586ec9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=267635196 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.267635196 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_ready_error.36749262
Short name T51
Test name
Test status
Simulation time 4400446770 ps
CPU time 49.86 seconds
Started Mar 24 01:58:20 PM PDT 24
Finished Mar 24 01:59:10 PM PDT 24
Peak memory 226760 kb
Host smart-ee6d5fbe-7dd8-411b-8296-62cc51613062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36749262 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.36749262 +enable_masking=
1 +sw_key_masked=0
Directory /workspace/8.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/8.kmac_entropy_refresh.1476980276
Short name T542
Test name
Test status
Simulation time 43781822654 ps
CPU time 112 seconds
Started Mar 24 01:58:19 PM PDT 24
Finished Mar 24 02:00:11 PM PDT 24
Peak memory 234300 kb
Host smart-f3bd4d9e-47e7-4dde-8fd8-1afa64753c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476980276 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.1476980276 +enable_masking=1 +s
w_key_masked=0
Directory /workspace/8.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/8.kmac_error.2111292221
Short name T247
Test name
Test status
Simulation time 1772036830 ps
CPU time 96.87 seconds
Started Mar 24 01:58:18 PM PDT 24
Finished Mar 24 01:59:55 PM PDT 24
Peak memory 243128 kb
Host smart-c860cc0a-2b1c-4a2d-88d1-44bd21cc1517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111292221 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.2111292221 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_error/latest

Test location /workspace/coverage/default/8.kmac_key_error.828313007
Short name T647
Test name
Test status
Simulation time 85288731 ps
CPU time 0.95 seconds
Started Mar 24 01:58:23 PM PDT 24
Finished Mar 24 01:58:25 PM PDT 24
Peak memory 218324 kb
Host smart-4d06314e-ff4e-4796-bf6e-28b4a1e486dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828313007 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.828313007 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_key_error/latest

Test location /workspace/coverage/default/8.kmac_lc_escalation.1834542891
Short name T20
Test name
Test status
Simulation time 77593487 ps
CPU time 1.66 seconds
Started Mar 24 01:58:23 PM PDT 24
Finished Mar 24 01:58:25 PM PDT 24
Peak memory 219504 kb
Host smart-17136216-dc92-4191-8fd4-4ab1d630e4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834542891 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.1834542891 +enable_masking=1 +sw_ke
y_masked=0
Directory /workspace/8.kmac_lc_escalation/latest

Test location /workspace/coverage/default/8.kmac_long_msg_and_output.3976570838
Short name T794
Test name
Test status
Simulation time 13614544538 ps
CPU time 1647.08 seconds
Started Mar 24 01:58:16 PM PDT 24
Finished Mar 24 02:25:43 PM PDT 24
Peak memory 352068 kb
Host smart-7842d05a-af65-4e79-989f-6d1dc0753b99
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976570838 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_a
nd_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_an
d_output.3976570838 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/8.kmac_mubi.4234178758
Short name T909
Test name
Test status
Simulation time 37117940060 ps
CPU time 441.31 seconds
Started Mar 24 01:58:20 PM PDT 24
Finished Mar 24 02:05:41 PM PDT 24
Peak memory 252800 kb
Host smart-0a14cdbe-bca3-44f8-85b7-936b9c26eeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234178758 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.4234178758 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_mubi/latest

Test location /workspace/coverage/default/8.kmac_sideload.3477838310
Short name T636
Test name
Test status
Simulation time 158302466769 ps
CPU time 365.44 seconds
Started Mar 24 01:58:18 PM PDT 24
Finished Mar 24 02:04:24 PM PDT 24
Peak memory 246736 kb
Host smart-50089cbc-a05a-4304-b76a-b22b2b2698e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477838310 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.3477838310 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_sideload/latest

Test location /workspace/coverage/default/8.kmac_smoke.3010510619
Short name T197
Test name
Test status
Simulation time 7646396780 ps
CPU time 77.91 seconds
Started Mar 24 01:58:16 PM PDT 24
Finished Mar 24 01:59:34 PM PDT 24
Peak memory 226672 kb
Host smart-0d1914fc-5390-4a68-bdf4-51a8e257d012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010510619 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.3010510619 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_smoke/latest

Test location /workspace/coverage/default/8.kmac_stress_all.2448862187
Short name T37
Test name
Test status
Simulation time 22138742211 ps
CPU time 1650.43 seconds
Started Mar 24 01:58:19 PM PDT 24
Finished Mar 24 02:25:49 PM PDT 24
Peak memory 406660 kb
Host smart-ecce262a-6d28-4f38-8101-a1da66225b36
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=2448862187 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all.2448862187 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_stress_all/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac.736169016
Short name T750
Test name
Test status
Simulation time 261289960 ps
CPU time 6.09 seconds
Started Mar 24 01:58:17 PM PDT 24
Finished Mar 24 01:58:23 PM PDT 24
Peak memory 218660 kb
Host smart-e713966e-4ccb-4d71-87cd-ecb1db5c516f
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736169016 -assert nopostproc +UVM_TESTNAME=kmac_base_
test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/
null -cm_name 8.kmac_test_vectors_kmac.736169016 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_kmac_xof.1969164078
Short name T224
Test name
Test status
Simulation time 297064906 ps
CPU time 6.57 seconds
Started Mar 24 01:58:17 PM PDT 24
Finished Mar 24 01:58:24 PM PDT 24
Peak memory 226736 kb
Host smart-e919b20e-dc4b-4dac-98a6-7aa3a1b8eb9c
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969164078 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 8.kmac_test_vectors_kmac_xof.1969164078 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_224.2372160313
Short name T379
Test name
Test status
Simulation time 756865846457 ps
CPU time 2577.77 seconds
Started Mar 24 01:58:18 PM PDT 24
Finished Mar 24 02:41:16 PM PDT 24
Peak memory 403244 kb
Host smart-289c2252-b798-4f03-abb8-f15952431541
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2372160313 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_224.2372160313 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_256.2300269148
Short name T967
Test name
Test status
Simulation time 63036656630 ps
CPU time 2131.83 seconds
Started Mar 24 01:58:22 PM PDT 24
Finished Mar 24 02:33:54 PM PDT 24
Peak memory 387576 kb
Host smart-34cb2c5f-8b13-4d4f-b400-cc70a587dcda
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2300269148 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_256.2300269148 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_384.195781206
Short name T633
Test name
Test status
Simulation time 61694220856 ps
CPU time 1498.96 seconds
Started Mar 24 01:58:17 PM PDT 24
Finished Mar 24 02:23:16 PM PDT 24
Peak memory 341544 kb
Host smart-1b0ff23c-dcd0-42f6-a3a5-47422a38d2a5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=195781206 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_384.195781206 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_sha3_512.844269232
Short name T337
Test name
Test status
Simulation time 226429738506 ps
CPU time 1361.75 seconds
Started Mar 24 01:58:18 PM PDT 24
Finished Mar 24 02:21:00 PM PDT 24
Peak memory 306172 kb
Host smart-f48704c8-7a70-4a48-97dc-65eacea58a1e
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=844269232 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_sha3_512.844269232 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_128.3583810517
Short name T630
Test name
Test status
Simulation time 276289975620 ps
CPU time 6243.09 seconds
Started Mar 24 01:58:16 PM PDT 24
Finished Mar 24 03:42:20 PM PDT 24
Peak memory 643624 kb
Host smart-1e2e9830-b6e6-4250-8d08-6c22523e8d91
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=3583810517 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_128.3583810517 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/8.kmac_test_vectors_shake_256.1822572306
Short name T214
Test name
Test status
Simulation time 56565083912 ps
CPU time 4338.51 seconds
Started Mar 24 01:58:17 PM PDT 24
Finished Mar 24 03:10:36 PM PDT 24
Peak memory 574388 kb
Host smart-5935f6ec-f1c2-4bc7-95e0-96e5605e4b36
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=1822572306 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_test_vectors_shake_256.1822572306 +enable_masking=1 +sw_key_masked=0
Directory /workspace/8.kmac_test_vectors_shake_256/latest

Test location /workspace/coverage/default/9.kmac_alert_test.3363572495
Short name T648
Test name
Test status
Simulation time 15157982 ps
CPU time 0.82 seconds
Started Mar 24 01:58:33 PM PDT 24
Finished Mar 24 01:58:34 PM PDT 24
Peak memory 220548 kb
Host smart-1a467bec-d847-43a7-bd73-f9ac5ff98937
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363572495 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.3363572495 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_alert_test/latest

Test location /workspace/coverage/default/9.kmac_app.814503410
Short name T451
Test name
Test status
Simulation time 41127944296 ps
CPU time 93.99 seconds
Started Mar 24 01:58:23 PM PDT 24
Finished Mar 24 01:59:58 PM PDT 24
Peak memory 231392 kb
Host smart-58bcb8e1-cee6-47fd-a8cc-61983a2d9770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814503410 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.814503410 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app/latest

Test location /workspace/coverage/default/9.kmac_app_with_partial_data.3463067226
Short name T1000
Test name
Test status
Simulation time 14716288901 ps
CPU time 323.56 seconds
Started Mar 24 01:58:24 PM PDT 24
Finished Mar 24 02:03:48 PM PDT 24
Peak memory 247372 kb
Host smart-7422492f-e648-44c2-8978-523d65b31b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463067226 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.3463067226 +enable_
masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_app_with_partial_data/latest

Test location /workspace/coverage/default/9.kmac_burst_write.3329099217
Short name T539
Test name
Test status
Simulation time 26270147088 ps
CPU time 1358.67 seconds
Started Mar 24 01:58:19 PM PDT 24
Finished Mar 24 02:20:58 PM PDT 24
Peak memory 243168 kb
Host smart-48059721-c884-42e8-8123-d35737cb42ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329099217 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.3329099217 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_burst_write/latest

Test location /workspace/coverage/default/9.kmac_edn_timeout_error.1294179594
Short name T141
Test name
Test status
Simulation time 105278272 ps
CPU time 3.75 seconds
Started Mar 24 01:58:29 PM PDT 24
Finished Mar 24 01:58:33 PM PDT 24
Peak memory 223740 kb
Host smart-9c857dc6-96a3-40ba-a252-4940f17db8be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1294179594 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.1294179594 +enabl
e_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_edn_timeout_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_mode_error.2328881389
Short name T916
Test name
Test status
Simulation time 21990569 ps
CPU time 0.97 seconds
Started Mar 24 01:58:29 PM PDT 24
Finished Mar 24 01:58:30 PM PDT 24
Peak memory 220460 kb
Host smart-215016ec-3c04-44dc-9a43-5a995943f3aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2328881389 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.2328881389 +ena
ble_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_mode_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_ready_error.4044553969
Short name T975
Test name
Test status
Simulation time 1173138219 ps
CPU time 12.86 seconds
Started Mar 24 01:58:29 PM PDT 24
Finished Mar 24 01:58:42 PM PDT 24
Peak memory 226756 kb
Host smart-813c2205-193f-48c6-ac3f-419e7111eae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044553969 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.4044553969 +enable_mask
ing=1 +sw_key_masked=0
Directory /workspace/9.kmac_entropy_ready_error/latest

Test location /workspace/coverage/default/9.kmac_entropy_refresh.428405130
Short name T879
Test name
Test status
Simulation time 3810217649 ps
CPU time 208.5 seconds
Started Mar 24 01:58:25 PM PDT 24
Finished Mar 24 02:01:54 PM PDT 24
Peak memory 243156 kb
Host smart-edafee7c-7603-4e63-bb4d-c4f0f65dbebf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428405130 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.428405130 +enable_masking=1 +sw_
key_masked=0
Directory /workspace/9.kmac_entropy_refresh/latest

Test location /workspace/coverage/default/9.kmac_error.2502235510
Short name T813
Test name
Test status
Simulation time 3792805113 ps
CPU time 79.21 seconds
Started Mar 24 01:58:28 PM PDT 24
Finished Mar 24 01:59:48 PM PDT 24
Peak memory 240436 kb
Host smart-ce1b6be5-fc72-4315-b486-ed6d7ca075f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502235510 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.2502235510 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_error/latest

Test location /workspace/coverage/default/9.kmac_key_error.1997488163
Short name T519
Test name
Test status
Simulation time 190415346 ps
CPU time 1.81 seconds
Started Mar 24 01:58:29 PM PDT 24
Finished Mar 24 01:58:31 PM PDT 24
Peak memory 218752 kb
Host smart-b71d8c19-07c1-4604-8957-5b7bfc6ca4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997488163 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.1997488163 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_key_error/latest

Test location /workspace/coverage/default/9.kmac_lc_escalation.265516757
Short name T817
Test name
Test status
Simulation time 122529015 ps
CPU time 1.31 seconds
Started Mar 24 01:58:27 PM PDT 24
Finished Mar 24 01:58:29 PM PDT 24
Peak memory 218652 kb
Host smart-23538ba4-32a0-4ca8-b056-26c2a896a495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=265516757 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.265516757 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_lc_escalation/latest

Test location /workspace/coverage/default/9.kmac_long_msg_and_output.56630935
Short name T193
Test name
Test status
Simulation time 9220159491 ps
CPU time 72.68 seconds
Started Mar 24 01:58:19 PM PDT 24
Finished Mar 24 01:59:31 PM PDT 24
Peak memory 226772 kb
Host smart-c243c79a-99d6-4aa3-876a-99595aedbdd8
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56630935 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and
_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_
output.56630935 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_long_msg_and_output/latest

Test location /workspace/coverage/default/9.kmac_mubi.193246224
Short name T790
Test name
Test status
Simulation time 14729366398 ps
CPU time 160.92 seconds
Started Mar 24 01:58:24 PM PDT 24
Finished Mar 24 02:01:05 PM PDT 24
Peak memory 239544 kb
Host smart-0774e9c4-a844-4cd8-917c-5eb7d1729729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193246224 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.193246224 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_mubi/latest

Test location /workspace/coverage/default/9.kmac_sideload.469995551
Short name T250
Test name
Test status
Simulation time 7304580794 ps
CPU time 234.45 seconds
Started Mar 24 01:58:20 PM PDT 24
Finished Mar 24 02:02:15 PM PDT 24
Peak memory 242392 kb
Host smart-be29c010-02f5-42c7-8437-b0eac263308a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469995551 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.469995551 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_sideload/latest

Test location /workspace/coverage/default/9.kmac_smoke.1726657906
Short name T516
Test name
Test status
Simulation time 1997694562 ps
CPU time 20.82 seconds
Started Mar 24 01:58:23 PM PDT 24
Finished Mar 24 01:58:44 PM PDT 24
Peak memory 226716 kb
Host smart-c7f5b3cd-19de-4c56-a517-5d257ccffca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726657906 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.1726657906 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_smoke/latest

Test location /workspace/coverage/default/9.kmac_stress_all.3069398864
Short name T410
Test name
Test status
Simulation time 116250417643 ps
CPU time 3174.73 seconds
Started Mar 24 01:58:33 PM PDT 24
Finished Mar 24 02:51:28 PM PDT 24
Peak memory 456772 kb
Host smart-fc927866-daa7-4b99-8af3-8b4b579fde3f
User root
Command /workspace/default/simv +test_timeout_ns=10_000_000_000 +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=1000000000
0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand
om_seed=3069398864 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all.3069398864 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_stress_all/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac.4230950218
Short name T262
Test name
Test status
Simulation time 417233804 ps
CPU time 5.35 seconds
Started Mar 24 01:58:27 PM PDT 24
Finished Mar 24 01:58:32 PM PDT 24
Peak memory 226672 kb
Host smart-7897edf6-5075-400b-996e-83cda8e352b5
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230950218 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev
/null -cm_name 9.kmac_test_vectors_kmac.4230950218 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_kmac_xof.3982158746
Short name T231
Test name
Test status
Simulation time 1080879775 ps
CPU time 5.67 seconds
Started Mar 24 01:58:23 PM PDT 24
Finished Mar 24 01:58:29 PM PDT 24
Peak memory 226712 kb
Host smart-f85a1f16-0b65-4ebd-9d1e-0385176ce3ff
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS
ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982158746 -assert nopostproc +UVM_TESTNAME=kmac_base
_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log
/dev/null -cm_name 9.kmac_test_vectors_kmac_xof.3982158746 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_kmac_xof/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_224.481881223
Short name T682
Test name
Test status
Simulation time 67771933426 ps
CPU time 2160.49 seconds
Started Mar 24 01:58:19 PM PDT 24
Finished Mar 24 02:34:19 PM PDT 24
Peak memory 388900 kb
Host smart-98e5201a-fca0-47f5-968a-e1b137997c3d
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
24 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=481881223 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_224.481881223 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_224/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_256.3687461127
Short name T223
Test name
Test status
Simulation time 19264381778 ps
CPU time 1848.66 seconds
Started Mar 24 01:58:23 PM PDT 24
Finished Mar 24 02:29:13 PM PDT 24
Peak memory 388220 kb
Host smart-be5ea0cd-35c9-4442-b614-1b6e2069c528
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=2
56 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3687461127 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_256.3687461127 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_256/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_384.2624520816
Short name T735
Test name
Test status
Simulation time 168331452815 ps
CPU time 1653.63 seconds
Started Mar 24 01:58:24 PM PDT 24
Finished Mar 24 02:25:58 PM PDT 24
Peak memory 342288 kb
Host smart-30c68535-45a9-47a2-980d-00d7987cabc2
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=3
84 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2624520816 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_384.2624520816 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_384/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_sha3_512.760114035
Short name T627
Test name
Test status
Simulation time 55279237043 ps
CPU time 1093.35 seconds
Started Mar 24 01:58:27 PM PDT 24
Finished Mar 24 02:16:41 PM PDT 24
Peak memory 299980 kb
Host smart-7ed2cda4-0fa4-482b-887b-439c9a2a7b85
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=5
12 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=760114035 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_sha3_512.760114035 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_sha3_512/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_128.495179561
Short name T386
Test name
Test status
Simulation time 272121135122 ps
CPU time 5162.01 seconds
Started Mar 24 01:58:23 PM PDT 24
Finished Mar 24 03:24:26 PM PDT 24
Peak memory 654164 kb
Host smart-365facf0-3be7-46da-a56b-598866de0b50
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=495179561 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_128.495179561 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_128/latest

Test location /workspace/coverage/default/9.kmac_test_vectors_shake_256.151390603
Short name T934
Test name
Test status
Simulation time 2117546276577 ps
CPU time 5489.03 seconds
Started Mar 24 01:58:24 PM PDT 24
Finished Mar 24 03:29:54 PM PDT 24
Peak memory 564832 kb
Host smart-b8b4eaec-9edd-4b32-8ed2-3acf3c6cc1f9
User root
Command /workspace/default/simv +test_vectors_dir=/workspace/default/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=
256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra
ndom_seed=151390603 -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_test_vectors_shake_256.151390603 +enable_masking=1 +sw_key_masked=0
Directory /workspace/9.kmac_test_vectors_shake_256/latest
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