Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	102489968	1			T1	259		T2	2500		T3	6
all_values[1]	102489968	1			T1	259		T2	2500		T3	6
all_values[2]	102489968	1			T1	259		T2	2500		T3	6

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

567533

1

T1

26

T2

3

T3

18

auto[1]

306902371

1

T1

751

T2

7497

T12

656172

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

305926899

1

T1

663

T2

7425

T3

18

auto[1]

1543005

1

T1

114

T2

75

T12

1758

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	168283	1			T2	1		T3	6		T6	81
all_values[0]	auto[0]	auto[1]	2133	1			T6	6		T7	4		T15	4
all_values[0]	auto[1]	auto[0]	101807350	1			T1	221		T2	2474		T12	218139
all_values[0]	auto[1]	auto[1]	512202	1			T1	38		T2	25		T12	586
all_values[1]	auto[0]	auto[0]	178521	1			T1	10		T2	2		T3	6
all_values[1]	auto[0]	auto[1]	1648	1			T1	3		T13	1		T6	4
all_values[1]	auto[1]	auto[0]	101797112	1			T1	211		T2	2473		T12	218139
all_values[1]	auto[1]	auto[1]	512687	1			T1	35		T2	25		T12	586
all_values[2]	auto[0]	auto[0]	215135	1			T1	10		T3	6		T12	2
all_values[2]	auto[0]	auto[1]	1813	1			T1	3		T12	1		T6	12
all_values[2]	auto[1]	auto[0]	101760498	1			T1	211		T2	2475		T12	218137
all_values[2]	auto[1]	auto[1]	512522	1			T1	35		T2	25		T12	585