Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
306896 |
1 |
|
|
T1 |
52 |
|
T2 |
50 |
|
T3 |
2 |
auto[1] |
393934 |
1 |
|
|
T12 |
778 |
|
T13 |
778 |
|
T7 |
108 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
175721 |
1 |
|
|
T1 |
16 |
|
T2 |
15 |
|
T12 |
203 |
lower_val |
173154 |
1 |
|
|
T1 |
8 |
|
T2 |
8 |
|
T12 |
180 |
zero_val |
1918 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
252306 |
1 |
|
|
T1 |
30 |
|
T2 |
26 |
|
T3 |
2 |
lower_val |
251946 |
1 |
|
|
T1 |
22 |
|
T2 |
24 |
|
T12 |
194 |
zero_val |
196578 |
1 |
|
|
T12 |
400 |
|
T13 |
362 |
|
T7 |
50 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
38439 |
1 |
|
|
T1 |
10 |
|
T2 |
4 |
|
T6 |
2 |
higher_val |
higher_val |
auto[1] |
24841 |
1 |
|
|
T12 |
47 |
|
T13 |
51 |
|
T7 |
7 |
higher_val |
lower_val |
auto[0] |
38512 |
1 |
|
|
T1 |
6 |
|
T2 |
11 |
|
T14 |
93 |
higher_val |
lower_val |
auto[1] |
24643 |
1 |
|
|
T12 |
44 |
|
T13 |
53 |
|
T7 |
3 |
higher_val |
zero_val |
auto[0] |
96 |
1 |
|
|
T8 |
1 |
|
T9 |
2 |
|
T178 |
1 |
higher_val |
zero_val |
auto[1] |
49190 |
1 |
|
|
T12 |
112 |
|
T13 |
94 |
|
T7 |
14 |
lower_val |
higher_val |
auto[0] |
37492 |
1 |
|
|
T1 |
4 |
|
T2 |
4 |
|
T6 |
2 |
lower_val |
higher_val |
auto[1] |
24656 |
1 |
|
|
T12 |
38 |
|
T13 |
52 |
|
T7 |
19 |
lower_val |
lower_val |
auto[0] |
37433 |
1 |
|
|
T1 |
4 |
|
T2 |
4 |
|
T6 |
2 |
lower_val |
lower_val |
auto[1] |
24821 |
1 |
|
|
T12 |
45 |
|
T13 |
51 |
|
T7 |
8 |
lower_val |
zero_val |
auto[0] |
88 |
1 |
|
|
T9 |
1 |
|
T20 |
1 |
|
T16 |
1 |
lower_val |
zero_val |
auto[1] |
48664 |
1 |
|
|
T12 |
97 |
|
T13 |
79 |
|
T7 |
18 |
zero_val |
higher_val |
auto[0] |
561 |
1 |
|
|
T3 |
1 |
|
T7 |
1 |
|
T14 |
1 |
zero_val |
higher_val |
auto[1] |
159 |
1 |
|
|
T12 |
1 |
|
T9 |
8 |
|
T93 |
1 |
zero_val |
lower_val |
auto[0] |
546 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T13 |
1 |
zero_val |
lower_val |
auto[1] |
146 |
1 |
|
|
T12 |
1 |
|
T93 |
1 |
|
T20 |
1 |
zero_val |
zero_val |
auto[0] |
271 |
1 |
|
|
T12 |
1 |
|
T8 |
1 |
|
T9 |
2 |
zero_val |
zero_val |
auto[1] |
235 |
1 |
|
|
T8 |
2 |
|
T9 |
3 |
|
T93 |
4 |