Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	102489968	1			T1	259		T2	2500		T3	6
all_pins[1]	102489968	1			T1	259		T2	2500		T3	6
all_pins[2]	102489968	1			T1	259		T2	2500		T3	6

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	306627193	1			T1	739		T2	7475		T3	18
values[0x1]	842711	1			T1	38		T2	25		T12	586
transitions[0x0=>0x1]	840503	1			T1	38		T2	25		T12	586
transitions[0x1=>0x0]	840527	1			T1	38		T2	25		T12	586

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	101977766	1			T1	221		T2	2475		T3	6
all_pins[0]	values[0x1]	512202	1			T1	38		T2	25		T12	586
all_pins[0]	transitions[0x0=>0x1]	512189	1			T1	38		T2	25		T12	586
all_pins[0]	transitions[0x1=>0x0]	6579	1			T7	28		T9	93		T70	8
all_pins[1]	values[0x0]	102483376	1			T1	259		T2	2500		T3	6
all_pins[1]	values[0x1]	6592	1			T7	28		T9	93		T70	8
all_pins[1]	transitions[0x0=>0x1]	6329	1			T7	28		T9	93		T70	8
all_pins[1]	transitions[0x1=>0x0]	323654	1			T7	119		T52	1436		T16	830
all_pins[2]	values[0x0]	102166051	1			T1	259		T2	2500		T3	6
all_pins[2]	values[0x1]	323917	1			T7	119		T52	1436		T16	830
all_pins[2]	transitions[0x0=>0x1]	321985	1			T7	119		T52	1436		T16	830
all_pins[2]	transitions[0x1=>0x0]	510294	1			T1	38		T2	25		T12	586