Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11316233 |
1 |
|
|
T1 |
913 |
|
T2 |
2970 |
|
T12 |
2730 |
auto[1] |
11316204 |
1 |
|
|
T1 |
913 |
|
T2 |
2970 |
|
T12 |
2730 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
22389947 |
1 |
|
|
T1 |
1794 |
|
T2 |
5920 |
|
T12 |
5460 |
triple_byte_access |
80266 |
1 |
|
|
T1 |
10 |
|
T2 |
6 |
|
T7 |
12 |
halfword_access |
81406 |
1 |
|
|
T1 |
10 |
|
T2 |
10 |
|
T7 |
22 |
byte_access |
80818 |
1 |
|
|
T1 |
12 |
|
T2 |
4 |
|
T7 |
32 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
11194988 |
1 |
|
|
T1 |
897 |
|
T2 |
2960 |
|
T12 |
2730 |
auto[0] |
triple_byte_access |
40133 |
1 |
|
|
T1 |
5 |
|
T2 |
3 |
|
T7 |
6 |
auto[0] |
halfword_access |
40703 |
1 |
|
|
T1 |
5 |
|
T2 |
5 |
|
T7 |
11 |
auto[0] |
byte_access |
40409 |
1 |
|
|
T1 |
6 |
|
T2 |
2 |
|
T7 |
16 |
auto[1] |
word_access |
11194959 |
1 |
|
|
T1 |
897 |
|
T2 |
2960 |
|
T12 |
2730 |
auto[1] |
triple_byte_access |
40133 |
1 |
|
|
T1 |
5 |
|
T2 |
3 |
|
T7 |
6 |
auto[1] |
halfword_access |
40703 |
1 |
|
|
T1 |
5 |
|
T2 |
5 |
|
T7 |
11 |
auto[1] |
byte_access |
40409 |
1 |
|
|
T1 |
6 |
|
T2 |
2 |
|
T7 |
16 |