Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100347006	1			T1	3081		T2	159530		T3	9110
all_values[1]	100347006	1			T1	3081		T2	159530		T3	9110
all_values[2]	100347006	1			T1	3081		T2	159530		T3	9110

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

575873

1

T1

606

T3

940

T5

1156

auto[1]

300465145

1

T1

8637

T2

478590

T3

26390

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299501955

1

T1

9171

T2

477192

T3

27054

auto[1]

1539063

1

T1

72

T2

1398

T3

276

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	186438	1			T1	200		T3	204		T5	260
all_values[0]	auto[0]	auto[1]	2022	1			T1	2		T3	2		T5	2
all_values[0]	auto[1]	auto[0]	99647547	1			T1	2857		T2	159064		T3	8814
all_values[0]	auto[1]	auto[1]	510999	1			T1	22		T2	466		T3	90
all_values[1]	auto[0]	auto[0]	176063	1			T1	200		T3	364		T5	444
all_values[1]	auto[0]	auto[1]	1580	1			T1	2		T3	3		T5	3
all_values[1]	auto[1]	auto[0]	99657922	1			T1	2857		T2	159064		T3	8654
all_values[1]	auto[1]	auto[1]	511441	1			T1	22		T2	466		T3	89
all_values[2]	auto[0]	auto[0]	208128	1			T1	200		T3	364		T5	444
all_values[2]	auto[0]	auto[1]	1642	1			T1	2		T3	3		T5	3
all_values[2]	auto[1]	auto[0]	99625857	1			T1	2857		T2	159064		T3	8654
all_values[2]	auto[1]	auto[1]	511379	1			T1	22		T2	466		T3	89