Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100347006	1			T1	3081		T2	159530		T3	9110
all_pins[1]	100347006	1			T1	3081		T2	159530		T3	9110
all_pins[2]	100347006	1			T1	3081		T2	159530		T3	9110

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300161193	1			T1	9221		T2	478124		T3	27031
values[0x1]	879825	1			T1	22		T2	466		T3	299
transitions[0x0=>0x1]	877163	1			T1	22		T2	466		T3	299
transitions[0x1=>0x0]	877187	1			T1	22		T2	466		T3	299

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99836007	1			T1	3059		T2	159064		T3	9020
all_pins[0]	values[0x1]	510999	1			T1	22		T2	466		T3	90
all_pins[0]	transitions[0x0=>0x1]	510989	1			T1	22		T2	466		T3	90
all_pins[0]	transitions[0x1=>0x0]	6257	1			T5	3		T6	77		T7	81
all_pins[1]	values[0x0]	100340739	1			T1	3081		T2	159530		T3	9110
all_pins[1]	values[0x1]	6267	1			T5	3		T6	77		T7	81
all_pins[1]	transitions[0x0=>0x1]	5939	1			T5	3		T6	75		T7	64
all_pins[1]	transitions[0x1=>0x0]	362231	1			T3	209		T6	1896		T7	6964
all_pins[2]	values[0x0]	99984447	1			T1	3081		T2	159530		T3	8901
all_pins[2]	values[0x1]	362559	1			T3	209		T6	1898		T7	6981
all_pins[2]	transitions[0x0=>0x1]	360235	1			T3	209		T6	1883		T7	6929
all_pins[2]	transitions[0x1=>0x0]	508699	1			T1	22		T2	466		T3	90