Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	698	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5612	1			T1	3		T3	7		T5	1
len_601_800	12857	1			T1	2		T3	21		T5	7
len_401_600	8293	1			T1	8		T3	11		T5	5
len_201_400	16598	1			T1	1		T3	4		T6	13
len_65_200	74355	1			T3	4		T9	685		T6	10
len_min_for_xof_require_squeeze	1006	1			T9	9		T17	10		T75	9
len_keccak_block_sizes[72]	748	1			T9	9		T6	1		T17	5
len_keccak_block_sizes[104]	765	1			T9	9		T17	5		T75	9
len_keccak_block_sizes[136]	759	1			T9	9		T17	5		T75	9
len_keccak_block_sizes[144]	286	1			T17	5		T130	1		T180	5
len_keccak_block_sizes[168]	284	1			T17	5		T7	1		T181	1
len_datapath_width	14193	1			T9	9		T6	5		T17	5
len_2_63	214428	1			T1	14		T2	310		T3	5
len_1	51	1			T182	1		T183	1		T184	1