Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
342462 |
1 |
|
|
T1 |
38 |
|
T2 |
303 |
|
T3 |
65 |
auto[1] |
3339 |
1 |
|
|
T1 |
3 |
|
T3 |
2 |
|
T5 |
9 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
307017 |
1 |
|
|
T1 |
30 |
|
T2 |
303 |
|
T3 |
17 |
auto[1] |
38784 |
1 |
|
|
T1 |
11 |
|
T3 |
50 |
|
T5 |
23 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
332695 |
1 |
|
|
T1 |
32 |
|
T2 |
303 |
|
T3 |
52 |
auto[1] |
13106 |
1 |
|
|
T1 |
9 |
|
T3 |
15 |
|
T5 |
14 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13106 |
1 |
|
|
T1 |
9 |
|
T3 |
15 |
|
T5 |
14 |
sw_kmac_invalid_sideload |
332695 |
1 |
|
|
T1 |
32 |
|
T2 |
303 |
|
T3 |
52 |
app_valid_sideload |
13106 |
1 |
|
|
T1 |
9 |
|
T3 |
15 |
|
T5 |
14 |
app_invalid_sideload |
332695 |
1 |
|
|
T1 |
32 |
|
T2 |
303 |
|
T3 |
52 |