Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg
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Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 0 8 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
share 2 0 2 100.00 100 1 1 2
state_read_mask 4 0 4 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
state_mask_share_cross 8 0 8 100.00 100 1 1 0


Summary for Variable share

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for share

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10869788 1 T1 2654 T2 3720 T3 10604
auto[1] 10869689 1 T1 2654 T2 3720 T3 10604



Summary for Variable state_read_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for state_read_mask

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
word_access 21498501 1 T1 5288 T2 7440 T3 21114
triple_byte_access 80108 1 T1 6 T3 22 T5 8
halfword_access 80680 1 T1 4 T3 30 T5 8
byte_access 80188 1 T1 10 T3 42 T5 8



Summary for Cross state_mask_share_cross

Samples crossed: share state_read_mask
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 0 8 100.00


Automatically Generated Cross Bins for state_mask_share_cross

Bins
sharestate_read_maskCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] word_access 10749300 1 T1 2644 T2 3720 T3 10557
auto[0] triple_byte_access 40054 1 T1 3 T3 11 T5 4
auto[0] halfword_access 40340 1 T1 2 T3 15 T5 4
auto[0] byte_access 40094 1 T1 5 T3 21 T5 4
auto[1] word_access 10749201 1 T1 2644 T2 3720 T3 10557
auto[1] triple_byte_access 40054 1 T1 3 T3 11 T5 4
auto[1] halfword_access 40340 1 T1 2 T3 15 T5 4
auto[1] byte_access 40094 1 T1 5 T3 21 T5 4

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