Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10869788 |
1 |
|
|
T1 |
2654 |
|
T2 |
3720 |
|
T3 |
10604 |
auto[1] |
10869689 |
1 |
|
|
T1 |
2654 |
|
T2 |
3720 |
|
T3 |
10604 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21498501 |
1 |
|
|
T1 |
5288 |
|
T2 |
7440 |
|
T3 |
21114 |
triple_byte_access |
80108 |
1 |
|
|
T1 |
6 |
|
T3 |
22 |
|
T5 |
8 |
halfword_access |
80680 |
1 |
|
|
T1 |
4 |
|
T3 |
30 |
|
T5 |
8 |
byte_access |
80188 |
1 |
|
|
T1 |
10 |
|
T3 |
42 |
|
T5 |
8 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10749300 |
1 |
|
|
T1 |
2644 |
|
T2 |
3720 |
|
T3 |
10557 |
auto[0] |
triple_byte_access |
40054 |
1 |
|
|
T1 |
3 |
|
T3 |
11 |
|
T5 |
4 |
auto[0] |
halfword_access |
40340 |
1 |
|
|
T1 |
2 |
|
T3 |
15 |
|
T5 |
4 |
auto[0] |
byte_access |
40094 |
1 |
|
|
T1 |
5 |
|
T3 |
21 |
|
T5 |
4 |
auto[1] |
word_access |
10749201 |
1 |
|
|
T1 |
2644 |
|
T2 |
3720 |
|
T3 |
10557 |
auto[1] |
triple_byte_access |
40054 |
1 |
|
|
T1 |
3 |
|
T3 |
11 |
|
T5 |
4 |
auto[1] |
halfword_access |
40340 |
1 |
|
|
T1 |
2 |
|
T3 |
15 |
|
T5 |
4 |
auto[1] |
byte_access |
40094 |
1 |
|
|
T1 |
5 |
|
T3 |
21 |
|
T5 |
4 |