Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99489245	1			T3	23610		T4	274		T5	251
all_values[1]	99489245	1			T3	23610		T4	274		T5	251
all_values[2]	99489245	1			T3	23610		T4	274		T5	251

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

586110

1

T3

330

T4

18

T5

18

auto[1]

297881625

1

T3

70500

T4

804

T5

735

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

296951430

1

T3

70122

T4

780

T5

720

auto[1]

1516305

1

T3

708

T4

42

T5

33

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	200256	1			T4	8		T6	7		T14	1
all_values[0]	auto[0]	auto[1]	2138	1			T4	4		T6	8		T14	2
all_values[0]	auto[1]	auto[0]	98783554	1			T3	23374		T4	252		T5	240
all_values[0]	auto[1]	auto[1]	503297	1			T3	236		T4	10		T5	11
all_values[1]	auto[0]	auto[0]	185175	1			T3	328		T5	10		T34	245
all_values[1]	auto[0]	auto[1]	1487	1			T3	2		T5	2		T34	3
all_values[1]	auto[1]	auto[0]	98798635	1			T3	23046		T4	260		T5	230
all_values[1]	auto[1]	auto[1]	503948	1			T3	234		T4	14		T5	9
all_values[2]	auto[0]	auto[0]	195378	1			T4	4		T5	5		T12	162
all_values[2]	auto[0]	auto[1]	1676	1			T4	2		T5	1		T12	1
all_values[2]	auto[1]	auto[0]	98788432	1			T3	23374		T4	256		T5	235
all_values[2]	auto[1]	auto[1]	503759	1			T3	236		T4	12		T5	10