Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
355596 |
1 |
|
|
T3 |
2 |
|
T4 |
18 |
|
T5 |
2 |
auto[1] |
331786 |
1 |
|
|
T3 |
334 |
|
T5 |
16 |
|
T13 |
490 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173032 |
1 |
|
|
T3 |
97 |
|
T4 |
2 |
|
T5 |
6 |
lower_val |
170371 |
1 |
|
|
T3 |
76 |
|
T4 |
4 |
|
T5 |
5 |
zero_val |
1830 |
1 |
|
|
T3 |
3 |
|
T4 |
1 |
|
T5 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
261844 |
1 |
|
|
T3 |
94 |
|
T4 |
8 |
|
T5 |
10 |
lower_val |
259388 |
1 |
|
|
T3 |
70 |
|
T4 |
10 |
|
T5 |
6 |
zero_val |
166150 |
1 |
|
|
T3 |
172 |
|
T5 |
2 |
|
T13 |
228 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
45047 |
1 |
|
|
T4 |
2 |
|
T12 |
43 |
|
T6 |
91 |
higher_val |
higher_val |
auto[1] |
20970 |
1 |
|
|
T3 |
29 |
|
T5 |
2 |
|
T13 |
33 |
higher_val |
lower_val |
auto[0] |
44466 |
1 |
|
|
T12 |
35 |
|
T6 |
85 |
|
T7 |
7 |
higher_val |
lower_val |
auto[1] |
20848 |
1 |
|
|
T3 |
18 |
|
T5 |
3 |
|
T13 |
34 |
higher_val |
zero_val |
auto[0] |
74 |
1 |
|
|
T5 |
1 |
|
T72 |
1 |
|
T33 |
2 |
higher_val |
zero_val |
auto[1] |
41627 |
1 |
|
|
T3 |
50 |
|
T13 |
77 |
|
T14 |
123 |
lower_val |
higher_val |
auto[0] |
44066 |
1 |
|
|
T4 |
1 |
|
T12 |
37 |
|
T6 |
98 |
lower_val |
higher_val |
auto[1] |
20822 |
1 |
|
|
T3 |
18 |
|
T5 |
4 |
|
T13 |
30 |
lower_val |
lower_val |
auto[0] |
43888 |
1 |
|
|
T4 |
3 |
|
T12 |
29 |
|
T6 |
100 |
lower_val |
lower_val |
auto[1] |
20401 |
1 |
|
|
T3 |
17 |
|
T5 |
1 |
|
T13 |
32 |
lower_val |
zero_val |
auto[0] |
80 |
1 |
|
|
T3 |
1 |
|
T45 |
1 |
|
T67 |
1 |
lower_val |
zero_val |
auto[1] |
41114 |
1 |
|
|
T3 |
40 |
|
T13 |
44 |
|
T14 |
106 |
zero_val |
higher_val |
auto[0] |
561 |
1 |
|
|
T12 |
1 |
|
T6 |
1 |
|
T7 |
1 |
zero_val |
higher_val |
auto[1] |
143 |
1 |
|
|
T55 |
1 |
|
T21 |
1 |
|
T39 |
3 |
zero_val |
lower_val |
auto[0] |
615 |
1 |
|
|
T4 |
1 |
|
T14 |
1 |
|
T8 |
1 |
zero_val |
lower_val |
auto[1] |
116 |
1 |
|
|
T39 |
1 |
|
T40 |
1 |
|
T179 |
1 |
zero_val |
zero_val |
auto[0] |
219 |
1 |
|
|
T3 |
1 |
|
T5 |
1 |
|
T79 |
1 |
zero_val |
zero_val |
auto[1] |
176 |
1 |
|
|
T3 |
2 |
|
T55 |
1 |
|
T39 |
1 |