Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99489245	1			T3	23610		T4	274		T5	251
all_pins[1]	99489245	1			T3	23610		T4	274		T5	251
all_pins[2]	99489245	1			T3	23610		T4	274		T5	251

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	297639893	1			T3	69375		T4	810		T5	742
values[0x1]	827842	1			T3	1455		T4	12		T5	11
transitions[0x0=>0x1]	825643	1			T3	1454		T4	12		T5	11
transitions[0x1=>0x0]	825672	1			T3	1455		T4	12		T5	11

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98985948	1			T3	23374		T4	264		T5	240
all_pins[0]	values[0x1]	503297	1			T3	236		T4	10		T5	11
all_pins[0]	transitions[0x0=>0x1]	503286	1			T3	236		T4	10		T5	11
all_pins[0]	transitions[0x1=>0x0]	5825	1			T4	2		T7	15		T8	1
all_pins[1]	values[0x0]	99483409	1			T3	23610		T4	272		T5	251
all_pins[1]	values[0x1]	5836	1			T4	2		T7	15		T8	1
all_pins[1]	transitions[0x0=>0x1]	5550	1			T4	2		T7	15		T8	1
all_pins[1]	transitions[0x1=>0x0]	318423	1			T3	1219		T12	911		T7	304
all_pins[2]	values[0x0]	99170536	1			T3	22391		T4	274		T5	251
all_pins[2]	values[0x1]	318709	1			T3	1219		T12	911		T7	304
all_pins[2]	transitions[0x0=>0x1]	316807	1			T3	1218		T12	911		T7	304
all_pins[2]	transitions[0x1=>0x0]	501424	1			T3	236		T4	10		T5	11