Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	675	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5564	1			T3	23		T12	22		T7	4
len_601_800	12839	1			T3	46		T12	37		T7	6
len_401_600	8288	1			T3	31		T12	24		T7	8
len_201_400	16300	1			T3	19		T12	14		T7	4
len_65_200	72901	1			T3	5		T12	5		T7	1
len_min_for_xof_require_squeeze	981	1			T66	10		T9	1		T69	1
len_keccak_block_sizes[72]	749	1			T21	3		T66	5		T69	3
len_keccak_block_sizes[104]	742	1			T66	5		T181	2		T180	5
len_keccak_block_sizes[136]	747	1			T21	1		T66	5		T39	2
len_keccak_block_sizes[144]	279	1			T66	5		T69	1		T180	5
len_keccak_block_sizes[168]	272	1			T21	2		T66	5		T180	5
len_datapath_width	14146	1			T4	3		T5	3		T13	246
len_2_63	211162	1			T3	8		T4	6		T5	6
len_1	43	1			T181	1		T182	1		T183	1