Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99478118	1			T2	17721		T3	2775		T4	18921
all_values[1]	99478118	1			T2	17721		T3	2775		T4	18921
all_values[2]	99478118	1			T2	17721		T3	2775		T4	18921

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

609888

1

T2

179

T4

637

T11

20

auto[1]

297824466

1

T2

52984

T3

8325

T4

56126

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

296920143

1

T2

52638

T3

7545

T4

56235

auto[1]

1514211

1

T2

525

T3

780

T4

528

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	205031	1			T2	177		T6	1		T12	34
all_values[0]	auto[0]	auto[1]	2383	1			T2	2		T6	2		T12	8
all_values[0]	auto[1]	auto[0]	98768350	1			T2	17369		T3	2515		T4	18745
all_values[0]	auto[1]	auto[1]	502354	1			T2	173		T3	260		T4	176
all_values[1]	auto[0]	auto[0]	168552	1			T4	632		T6	4		T38	165
all_values[1]	auto[0]	auto[1]	1666	1			T4	5		T6	3		T38	3
all_values[1]	auto[1]	auto[0]	98804829	1			T2	17546		T3	2515		T4	18113
all_values[1]	auto[1]	auto[1]	503071	1			T2	175		T3	260		T4	171
all_values[2]	auto[0]	auto[0]	230526	1			T11	13		T39	3		T14	589
all_values[2]	auto[0]	auto[1]	1730	1			T11	7		T39	4		T14	12
all_values[2]	auto[1]	auto[0]	98742855	1			T2	17546		T3	2515		T4	18745
all_values[2]	auto[1]	auto[1]	503007	1			T2	175		T3	260		T4	176