Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
341282 |
1 |
|
|
T2 |
2 |
|
T3 |
2 |
|
T4 |
266 |
auto[1] |
345106 |
1 |
|
|
T2 |
398 |
|
T3 |
352 |
|
T12 |
238 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
171225 |
1 |
|
|
T2 |
99 |
|
T3 |
88 |
|
T4 |
58 |
lower_val |
169681 |
1 |
|
|
T2 |
104 |
|
T3 |
103 |
|
T4 |
48 |
zero_val |
1939 |
1 |
|
|
T2 |
1 |
|
T3 |
1 |
|
T4 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
255300 |
1 |
|
|
T2 |
110 |
|
T3 |
90 |
|
T4 |
128 |
lower_val |
257844 |
1 |
|
|
T2 |
86 |
|
T3 |
82 |
|
T4 |
138 |
zero_val |
173244 |
1 |
|
|
T2 |
204 |
|
T3 |
182 |
|
T12 |
130 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
42235 |
1 |
|
|
T4 |
23 |
|
T11 |
92 |
|
T6 |
110 |
higher_val |
higher_val |
auto[1] |
21573 |
1 |
|
|
T2 |
27 |
|
T3 |
28 |
|
T12 |
9 |
higher_val |
lower_val |
auto[0] |
42817 |
1 |
|
|
T4 |
35 |
|
T11 |
82 |
|
T6 |
104 |
higher_val |
lower_val |
auto[1] |
21532 |
1 |
|
|
T2 |
20 |
|
T3 |
20 |
|
T12 |
16 |
higher_val |
zero_val |
auto[0] |
74 |
1 |
|
|
T14 |
1 |
|
T8 |
1 |
|
T23 |
3 |
higher_val |
zero_val |
auto[1] |
42994 |
1 |
|
|
T2 |
52 |
|
T3 |
40 |
|
T12 |
45 |
lower_val |
higher_val |
auto[0] |
41546 |
1 |
|
|
T3 |
1 |
|
T4 |
25 |
|
T11 |
108 |
lower_val |
higher_val |
auto[1] |
21191 |
1 |
|
|
T2 |
27 |
|
T3 |
20 |
|
T12 |
17 |
lower_val |
lower_val |
auto[0] |
42469 |
1 |
|
|
T4 |
23 |
|
T11 |
102 |
|
T6 |
104 |
lower_val |
lower_val |
auto[1] |
21437 |
1 |
|
|
T2 |
21 |
|
T3 |
24 |
|
T12 |
17 |
lower_val |
zero_val |
auto[0] |
86 |
1 |
|
|
T2 |
1 |
|
T14 |
2 |
|
T34 |
1 |
lower_val |
zero_val |
auto[1] |
42952 |
1 |
|
|
T2 |
55 |
|
T3 |
58 |
|
T12 |
34 |
zero_val |
higher_val |
auto[0] |
546 |
1 |
|
|
T3 |
1 |
|
T6 |
1 |
|
T39 |
1 |
zero_val |
higher_val |
auto[1] |
176 |
1 |
|
|
T38 |
1 |
|
T14 |
2 |
|
T124 |
1 |
zero_val |
lower_val |
auto[0] |
572 |
1 |
|
|
T4 |
1 |
|
T11 |
1 |
|
T12 |
1 |
zero_val |
lower_val |
auto[1] |
160 |
1 |
|
|
T14 |
3 |
|
T31 |
7 |
|
T8 |
1 |
zero_val |
zero_val |
auto[0] |
247 |
1 |
|
|
T2 |
1 |
|
T13 |
1 |
|
T14 |
3 |
zero_val |
zero_val |
auto[1] |
238 |
1 |
|
|
T14 |
1 |
|
T31 |
5 |
|
T124 |
1 |