Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99478118	1			T2	17721		T3	2775		T4	18921
all_pins[1]	99478118	1			T2	17721		T3	2775		T4	18921
all_pins[2]	99478118	1			T2	17721		T3	2775		T4	18921

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	297630848	1			T2	52958		T3	8037		T4	55479
values[0x1]	803506	1			T2	205		T3	288		T4	1284
transitions[0x0=>0x1]	801307	1			T2	205		T3	288		T4	1284
transitions[0x1=>0x0]	801331	1			T2	205		T3	288		T4	1284

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98975764	1			T2	17548		T3	2515		T4	18745
all_pins[0]	values[0x1]	502354	1			T2	173		T3	260		T4	176
all_pins[0]	transitions[0x0=>0x1]	502340	1			T2	173		T3	260		T4	176
all_pins[0]	transitions[0x1=>0x0]	6598	1			T2	32		T3	28		T7	10
all_pins[1]	values[0x0]	99471506	1			T2	17689		T3	2747		T4	18921
all_pins[1]	values[0x1]	6612	1			T2	32		T3	28		T7	10
all_pins[1]	transitions[0x0=>0x1]	6239	1			T2	32		T3	28		T7	10
all_pins[1]	transitions[0x1=>0x0]	294167	1			T4	1108		T14	1824		T33	196
all_pins[2]	values[0x0]	99183578	1			T2	17721		T3	2775		T4	17813
all_pins[2]	values[0x1]	294540	1			T4	1108		T14	1824		T33	196
all_pins[2]	transitions[0x0=>0x1]	292728	1			T4	1108		T14	1812		T33	195
all_pins[2]	transitions[0x1=>0x0]	500566	1			T2	173		T3	260		T4	176