Summary for Variable in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for in_app_keymgr
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
336961 |
1 |
|
|
T2 |
248 |
|
T3 |
176 |
|
T4 |
138 |
auto[1] |
3219 |
1 |
|
|
T2 |
36 |
|
T4 |
2 |
|
T5 |
1 |
Summary for Variable kmac_mode
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for kmac_mode
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
302967 |
1 |
|
|
T2 |
165 |
|
T3 |
46 |
|
T4 |
41 |
auto[1] |
37213 |
1 |
|
|
T2 |
119 |
|
T3 |
130 |
|
T4 |
99 |
Summary for Variable sideload
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for sideload
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
326737 |
1 |
|
|
T2 |
215 |
|
T3 |
176 |
|
T4 |
121 |
auto[1] |
13443 |
1 |
|
|
T2 |
69 |
|
T4 |
19 |
|
T5 |
1 |
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
User Defined Cross Bins |
4 |
0 |
4 |
100.00 |
|
User Defined Cross Bins for sideload_cross
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
sw_kmac_valid_sideload |
13443 |
1 |
|
|
T2 |
69 |
|
T4 |
19 |
|
T5 |
1 |
sw_kmac_invalid_sideload |
326737 |
1 |
|
|
T2 |
215 |
|
T3 |
176 |
|
T4 |
121 |
app_valid_sideload |
13443 |
1 |
|
|
T2 |
69 |
|
T4 |
19 |
|
T5 |
1 |
app_invalid_sideload |
326737 |
1 |
|
|
T2 |
215 |
|
T3 |
176 |
|
T4 |
121 |