Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10589118 |
1 |
|
|
T2 |
23519 |
|
T3 |
29699 |
|
T4 |
19696 |
auto[1] |
10589094 |
1 |
|
|
T2 |
23519 |
|
T3 |
29699 |
|
T4 |
19696 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20942194 |
1 |
|
|
T2 |
46876 |
|
T3 |
59136 |
|
T4 |
39212 |
triple_byte_access |
78698 |
1 |
|
|
T2 |
44 |
|
T3 |
92 |
|
T4 |
60 |
halfword_access |
78980 |
1 |
|
|
T2 |
52 |
|
T3 |
96 |
|
T4 |
68 |
byte_access |
78340 |
1 |
|
|
T2 |
66 |
|
T3 |
74 |
|
T4 |
52 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10471109 |
1 |
|
|
T2 |
23438 |
|
T3 |
29568 |
|
T4 |
19606 |
auto[0] |
triple_byte_access |
39349 |
1 |
|
|
T2 |
22 |
|
T3 |
46 |
|
T4 |
30 |
auto[0] |
halfword_access |
39490 |
1 |
|
|
T2 |
26 |
|
T3 |
48 |
|
T4 |
34 |
auto[0] |
byte_access |
39170 |
1 |
|
|
T2 |
33 |
|
T3 |
37 |
|
T4 |
26 |
auto[1] |
word_access |
10471085 |
1 |
|
|
T2 |
23438 |
|
T3 |
29568 |
|
T4 |
19606 |
auto[1] |
triple_byte_access |
39349 |
1 |
|
|
T2 |
22 |
|
T3 |
46 |
|
T4 |
30 |
auto[1] |
halfword_access |
39490 |
1 |
|
|
T2 |
26 |
|
T3 |
48 |
|
T4 |
34 |
auto[1] |
byte_access |
39170 |
1 |
|
|
T2 |
33 |
|
T3 |
37 |
|
T4 |
26 |