Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 7 0 7 100.00
Crosses 12 0 12 100.00


Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_cg_cc 12 0 12 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 98872927 1 T1 16105 T2 566206 T4 109301
all_values[1] 98872927 1 T1 16105 T2 566206 T4 109301
all_values[2] 98872927 1 T1 16105 T2 566206 T4 109301



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 469417 1 T1 3 T2 3 T4 10
auto[1] 296149364 1 T1 48312 T2 169861 T4 327893



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 295109493 1 T1 47832 T2 168822 T4 326811
auto[1] 1509288 1 T1 483 T2 10389 T4 1092



Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 12 0 12 100.00


Automatically Generated Cross Bins for intr_cg_cc

Bins
cp_intrcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] 146415 1 T1 1 T2 1 T5 2965
all_values[0] auto[0] auto[1] 2084 1 T2 2 T5 2 T10 2
all_values[0] auto[1] auto[0] 98223416 1 T1 15943 T2 562742 T4 108937
all_values[0] auto[1] auto[1] 501012 1 T1 161 T2 3461 T4 364
all_values[1] auto[0] auto[0] 185653 1 T1 2 T4 2 T5 6186
all_values[1] auto[0] auto[1] 1600 1 T4 1 T5 7 T12 1
all_values[1] auto[1] auto[0] 98184178 1 T1 15942 T2 562743 T4 108935
all_values[1] auto[1] auto[1] 501496 1 T1 161 T2 3463 T4 363
all_values[2] auto[0] auto[0] 132115 1 T4 4 T5 3265 T14 1
all_values[2] auto[0] auto[1] 1550 1 T4 3 T5 6 T56 2
all_values[2] auto[1] auto[0] 98237716 1 T1 15944 T2 562743 T4 108933
all_values[2] auto[1] auto[1] 501546 1 T1 161 T2 3463 T4 361

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