Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
337410 |
1 |
|
|
T1 |
294 |
|
T2 |
4674 |
|
T4 |
492 |
auto[1] |
347554 |
1 |
|
|
T5 |
270 |
|
T10 |
4528 |
|
T12 |
490 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
171002 |
1 |
|
|
T1 |
78 |
|
T2 |
1177 |
|
T4 |
109 |
lower_val |
169476 |
1 |
|
|
T1 |
79 |
|
T2 |
1142 |
|
T4 |
134 |
zero_val |
1843 |
1 |
|
|
T1 |
1 |
|
T2 |
9 |
|
T4 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
254590 |
1 |
|
|
T1 |
156 |
|
T2 |
2334 |
|
T4 |
244 |
lower_val |
255956 |
1 |
|
|
T1 |
138 |
|
T2 |
2340 |
|
T4 |
248 |
zero_val |
174418 |
1 |
|
|
T5 |
128 |
|
T10 |
2210 |
|
T12 |
230 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
42137 |
1 |
|
|
T1 |
47 |
|
T2 |
586 |
|
T4 |
60 |
higher_val |
higher_val |
auto[1] |
21554 |
1 |
|
|
T5 |
15 |
|
T10 |
286 |
|
T12 |
37 |
higher_val |
lower_val |
auto[0] |
41853 |
1 |
|
|
T1 |
31 |
|
T2 |
591 |
|
T4 |
49 |
higher_val |
lower_val |
auto[1] |
21975 |
1 |
|
|
T5 |
20 |
|
T10 |
306 |
|
T12 |
46 |
higher_val |
zero_val |
auto[0] |
97 |
1 |
|
|
T65 |
1 |
|
T29 |
1 |
|
T26 |
1 |
higher_val |
zero_val |
auto[1] |
43386 |
1 |
|
|
T5 |
40 |
|
T10 |
526 |
|
T12 |
64 |
lower_val |
higher_val |
auto[0] |
41689 |
1 |
|
|
T1 |
32 |
|
T2 |
539 |
|
T4 |
68 |
lower_val |
higher_val |
auto[1] |
21366 |
1 |
|
|
T5 |
7 |
|
T10 |
269 |
|
T12 |
19 |
lower_val |
lower_val |
auto[0] |
41982 |
1 |
|
|
T1 |
47 |
|
T2 |
603 |
|
T4 |
66 |
lower_val |
lower_val |
auto[1] |
21515 |
1 |
|
|
T5 |
16 |
|
T10 |
313 |
|
T12 |
41 |
lower_val |
zero_val |
auto[0] |
77 |
1 |
|
|
T31 |
1 |
|
T188 |
1 |
|
T29 |
1 |
lower_val |
zero_val |
auto[1] |
42847 |
1 |
|
|
T5 |
20 |
|
T10 |
586 |
|
T12 |
56 |
zero_val |
higher_val |
auto[0] |
577 |
1 |
|
|
T1 |
1 |
|
T2 |
4 |
|
T4 |
1 |
zero_val |
higher_val |
auto[1] |
140 |
1 |
|
|
T189 |
1 |
|
T190 |
1 |
|
T191 |
1 |
zero_val |
lower_val |
auto[0] |
493 |
1 |
|
|
T2 |
5 |
|
T4 |
2 |
|
T57 |
1 |
zero_val |
lower_val |
auto[1] |
137 |
1 |
|
|
T5 |
3 |
|
T29 |
2 |
|
T192 |
1 |
zero_val |
zero_val |
auto[0] |
273 |
1 |
|
|
T5 |
1 |
|
T12 |
1 |
|
T13 |
1 |
zero_val |
zero_val |
auto[1] |
223 |
1 |
|
|
T189 |
1 |
|
T192 |
1 |
|
T107 |
1 |