Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

Group : kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msgfifo_level_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
hash_mode	3	0	3	100.00	100	1	1	0
kmac_mode	2	0	2	100.00	100	1	1	2
msgfifo_depth	11	0	11	100.00	100	1	1	0
msgfifo_empty	2	0	2	100.00	100	1	1	2
msgfifo_full	2	0	2	100.00	100	1	1	2

Summary for Variable hash_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for hash_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
cshake	16066300	1			T1	11405		T5	62570		T14	52
shake	56555631	1			T1	10047		T2	561531		T5	26890
sha3	34808640	1			T1	194		T4	108808		T5	37

---

Summary for Variable kmac_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_mode

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

91363078

1

T1

10237

T2

561531

T4

108808

auto[1]

16067493

1

T1

11409

T5

62579

T14

83

---

Summary for Variable msgfifo_depth

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for msgfifo_depth

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
depth[0x00]	91158230	1			T1	20934		T2	447222		T4	53750
depth[0x01]	3750569	1			T1	516		T2	25303		T4	11918
depth[0x02]	3159317	1			T1	126		T2	27880		T4	13023
depth[0x03]	2947058	1			T1	61		T2	26101		T4	12166
depth[0x04]	2636715	1			T1	9		T2	23705		T4	11886
depth[0x05]	1512848	1			T2	11317		T4	6064		T5	3217
depth[0x06]	463419	1			T2	3		T4	1		T5	2496
depth[0x07]	379754	1			T5	2150		T6	11		T9	2
depth[0x08]	372547	1			T5	2117		T6	13		T9	2
depth[0x09]	352964	1			T5	2022		T6	6		T9	3
depth[0x0a]	697150	1			T5	4315		T6	74		T9	176

---

Summary for Variable msgfifo_empty

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_empty

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16272341

1

T1

712

T2

114309

T4

55058

auto[1]

91158230

1

T1

20934

T2

447222

T4

53750

---

Summary for Variable msgfifo_full

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msgfifo_full

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

106733421

1

T1

21646

T2

561531

T4

108808

auto[1]

697150

1

T5

4315

T6

74

T9

176