Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	98872927	1			T1	16105		T2	566206		T4	109301
all_pins[1]	98872927	1			T1	16105		T2	566206		T4	109301
all_pins[2]	98872927	1			T1	16105		T2	566206		T4	109301

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	295812726	1			T1	48154		T2	169515		T4	327539
values[0x1]	806055	1			T1	161		T2	3461		T4	364
transitions[0x0=>0x1]	804060	1			T1	161		T2	3461		T4	364
transitions[0x1=>0x0]	804079	1			T1	161		T2	3461		T4	364

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	98371915	1			T1	15944		T2	562745		T4	108937
all_pins[0]	values[0x1]	501012	1			T1	161		T2	3461		T4	364
all_pins[0]	transitions[0x0=>0x1]	500997	1			T1	161		T2	3461		T4	364
all_pins[0]	transitions[0x1=>0x0]	5255	1			T5	52		T6	2		T9	1
all_pins[1]	values[0x0]	98867657	1			T1	16105		T2	566206		T4	109301
all_pins[1]	values[0x1]	5270	1			T5	52		T6	2		T9	1
all_pins[1]	transitions[0x0=>0x1]	5119	1			T5	52		T6	2		T9	1
all_pins[1]	transitions[0x1=>0x0]	299622	1			T36	947		T16	20921		T37	1126
all_pins[2]	values[0x0]	98573154	1			T1	16105		T2	566206		T4	109301
all_pins[2]	values[0x1]	299773	1			T36	947		T16	20921		T37	1126
all_pins[2]	transitions[0x0=>0x1]	297944	1			T36	947		T16	20790		T37	1126
all_pins[2]	transitions[0x1=>0x0]	499202	1			T1	161		T2	3461		T4	364