Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	629	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5553	1			T1	15		T5	32		T44	6
len_601_800	12553	1			T1	48		T5	56		T44	16
len_401_600	8367	1			T1	26		T5	23		T44	13
len_201_400	16130	1			T1	11		T5	19		T10	251
len_65_200	72921	1			T1	6		T2	685		T5	25
len_min_for_xof_require_squeeze	978	1			T2	9		T5	1		T10	10
len_keccak_block_sizes[72]	738	1			T2	9		T10	5		T193	9
len_keccak_block_sizes[104]	747	1			T2	9		T10	5		T44	1
len_keccak_block_sizes[136]	740	1			T2	9		T10	5		T193	9
len_keccak_block_sizes[144]	279	1			T10	5		T194	1		T81	1
len_keccak_block_sizes[168]	292	1			T10	5		T37	2		T115	1
len_datapath_width	14035	1			T2	9		T4	246		T5	1
len_2_63	210487	1			T1	39		T2	1643		T5	73
len_1	67	1			T147	1		T118	2		T190	1