Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10695826 |
1 |
|
|
T1 |
20353 |
|
T2 |
27235 |
|
T4 |
3936 |
auto[1] |
10695818 |
1 |
|
|
T1 |
20353 |
|
T2 |
27235 |
|
T4 |
3936 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21155402 |
1 |
|
|
T1 |
40534 |
|
T2 |
52796 |
|
T4 |
7872 |
triple_byte_access |
78510 |
1 |
|
|
T1 |
64 |
|
T2 |
558 |
|
T5 |
96 |
halfword_access |
79218 |
1 |
|
|
T1 |
42 |
|
T2 |
558 |
|
T5 |
90 |
byte_access |
78514 |
1 |
|
|
T1 |
66 |
|
T2 |
558 |
|
T5 |
100 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10577705 |
1 |
|
|
T1 |
20267 |
|
T2 |
26398 |
|
T4 |
3936 |
auto[0] |
triple_byte_access |
39255 |
1 |
|
|
T1 |
32 |
|
T2 |
279 |
|
T5 |
48 |
auto[0] |
halfword_access |
39609 |
1 |
|
|
T1 |
21 |
|
T2 |
279 |
|
T5 |
45 |
auto[0] |
byte_access |
39257 |
1 |
|
|
T1 |
33 |
|
T2 |
279 |
|
T5 |
50 |
auto[1] |
word_access |
10577697 |
1 |
|
|
T1 |
20267 |
|
T2 |
26398 |
|
T4 |
3936 |
auto[1] |
triple_byte_access |
39255 |
1 |
|
|
T1 |
32 |
|
T2 |
279 |
|
T5 |
48 |
auto[1] |
halfword_access |
39609 |
1 |
|
|
T1 |
21 |
|
T2 |
279 |
|
T5 |
45 |
auto[1] |
byte_access |
39257 |
1 |
|
|
T1 |
33 |
|
T2 |
279 |
|
T5 |
50 |