Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100157803	1			T1	229654		T3	1917		T4	456139
all_values[1]	100157803	1			T1	229654		T3	1917		T4	456139
all_values[2]	100157803	1			T1	229654		T3	1917		T4	456139

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

668593

1

T3

6

T4

7

T5

92

auto[1]

299804816

1

T1

688962

T3

5745

T4

136841

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298960029

1

T1

688317

T3

5226

T4

135813

auto[1]

1513380

1

T1

645

T3

525

T4

10284

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	219155	1			T4	3		T5	52		T11	7
all_values[0]	auto[0]	auto[1]	2080	1			T4	4		T5	10		T11	2
all_values[0]	auto[1]	auto[0]	99434188	1			T1	229439		T3	1742		T4	452708
all_values[0]	auto[1]	auto[1]	502380	1			T1	215		T3	175		T4	3424
all_values[1]	auto[0]	auto[0]	219226	1			T3	2		T5	13		T6	2996
all_values[1]	auto[0]	auto[1]	1609	1			T3	1		T5	2		T6	3
all_values[1]	auto[1]	auto[0]	99434117	1			T1	229439		T3	1740		T4	452711
all_values[1]	auto[1]	auto[1]	502851	1			T1	215		T3	174		T4	3428
all_values[2]	auto[0]	auto[0]	224876	1			T3	2		T5	13		T6	2996
all_values[2]	auto[0]	auto[1]	1647	1			T3	1		T5	2		T6	3
all_values[2]	auto[1]	auto[0]	99428467	1			T1	229439		T3	1740		T4	452711
all_values[2]	auto[1]	auto[1]	502813	1			T1	215		T3	174		T4	3428