Unified Coverage Report :: Group :: kmac_env_pkg::config_masked_cg

Group : kmac_env_pkg::config_masked_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.88	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::config_masked_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	28	1	27	96.43
Crosses	4	0	4	100.00

Variables for Group kmac_env_pkg::config_masked_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
entropy_fast_process	2	0	2	100.00	100	1	1	2
entropy_mode	3	1	2	66.67	100	1	1	0
key_len	5	0	5	100.00	100	1	1	0
kmac_en	2	0	2	100.00	100	1	1	2
mode	3	0	3	100.00	100	1	1	0
msg_endian	2	0	2	100.00	100	1	1	2
sideload	2	0	2	100.00	100	1	1	2
state_endian	2	0	2	100.00	100	1	1	2
strength	5	0	5	100.00	100	1	1	0
xof_en	2	0	2	100.00	100	1	1	2

Crosses for Group kmac_env_pkg::config_masked_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
kmac_cross	1	0	1	100.00	100	1	1	0
cshake_cross	1	0	1	100.00	100	1	1	0
shake_cross	1	0	1	100.00	100	1	1	0
sha3_cross	1	0	1	100.00	100	1	1	0

Summary for Variable entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for entropy_fast_process

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

170865

1

T1

70

T3

63

T4

1129

auto[1]

171311

1

T1

74

T3

59

T4

1136

---

Summary for Variable entropy_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	1	2	66.67

Automatically Generated Bins for entropy_mode

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[EntropyModeNone]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[EntropyModeEdn]

153969

1

T3

122

T4

2265

T36

65

auto[EntropyModeSw]

188207

1

T1

144

T5

46

T6

157

---

Summary for Variable key_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for key_len

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[Key128]	65048	1			T1	27		T3	23		T4	412
auto[Key192]	65314	1			T1	30		T3	23		T4	465
auto[Key256]	80915	1			T1	25		T3	29		T4	459
auto[Key384]	65228	1			T1	37		T3	26		T4	465
auto[Key512]	65671	1			T1	25		T3	21		T4	464

---

Summary for Variable kmac_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

306496

1

T1

40

T3

28

T4

2265

auto[1]

35680

1

T1

104

T3

94

T5

36

---

Summary for Variable mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	3	0	3	100.00

Automatically Generated Bins for mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[Sha3]	67088	1			T1	2		T3	3		T5	9
auto[Shake]	235919	1			T1	38		T3	25		T4	2265
auto[CShake]	39169	1			T1	104		T3	94		T5	36

---

Summary for Variable msg_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for msg_endian

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171614

1

T1

59

T3

59

T4

1142

auto[1]

170562

1

T1

85

T3

63

T4

1123

---

Summary for Variable sideload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for sideload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

331258

1

T1

144

T3

122

T4

2265

auto[1]

10918

1

T12

26

T36

86

T61

10

---

Summary for Variable state_endian

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for state_endian

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

171081

1

T1

88

T3

70

T4

1165

auto[1]

171095

1

T1

56

T3

52

T4

1100

---

Summary for Variable strength

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for strength

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[L128]	138642	1			T1	61		T3	64		T5	16
auto[L224]	19479	1			T3	1		T5	4		T6	1
auto[L256]	155472	1			T1	81		T3	55		T4	2265
auto[L384]	15889	1			T1	2		T3	2		T5	3
auto[L512]	12694	1			T5	2		T11	2		T12	1

---

Summary for Variable xof_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for xof_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

321970

1

T1

75

T3

57

T4

2265

auto[1]

20206

1

T1

69

T3

65

T5

26

---

Summary for Cross kmac_cross

Samples crossed: kmac_en xof_en strength key_len msg_endian state_endian entropy_mode entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for kmac_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

35680

1

T1

104

T3

94

T5

36

---

Summary for Cross cshake_cross

Samples crossed: mode strength msg_endian state_endian entropy_mode entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for cshake_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

39169

1

T1

104

T3

94

T5

36

---

Summary for Cross shake_cross

Samples crossed: mode strength msg_endian state_endian entropy_mode entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for shake_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

235919

1

T1

38

T3

25

T4

2265

---

Summary for Cross sha3_cross

Samples crossed: mode strength msg_endian state_endian entropy_mode entropy_fast_process

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
User Defined Cross Bins	1	0	1	100.00

User Defined Cross Bins for sha3_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid_mode	0	Excluded
invalid_strength	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valid

67088

1

T1

2

T3

3

T5

9