Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
379200 |
1 |
|
|
T1 |
288 |
|
T2 |
2 |
|
T3 |
2 |
auto[1] |
308140 |
1 |
|
|
T3 |
242 |
|
T4 |
4528 |
|
T36 |
130 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
172054 |
1 |
|
|
T1 |
65 |
|
T3 |
53 |
|
T4 |
1190 |
lower_val |
170451 |
1 |
|
|
T1 |
94 |
|
T3 |
76 |
|
T4 |
1230 |
zero_val |
1883 |
1 |
|
|
T1 |
1 |
|
T2 |
2 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
266434 |
1 |
|
|
T1 |
144 |
|
T3 |
56 |
|
T4 |
1138 |
lower_val |
266566 |
1 |
|
|
T1 |
144 |
|
T2 |
2 |
|
T3 |
60 |
zero_val |
154340 |
1 |
|
|
T3 |
128 |
|
T4 |
2246 |
|
T36 |
64 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
47191 |
1 |
|
|
T1 |
27 |
|
T5 |
8 |
|
T6 |
33 |
higher_val |
higher_val |
auto[1] |
19330 |
1 |
|
|
T3 |
11 |
|
T4 |
290 |
|
T36 |
5 |
higher_val |
lower_val |
auto[0] |
47340 |
1 |
|
|
T1 |
38 |
|
T5 |
12 |
|
T6 |
35 |
higher_val |
lower_val |
auto[1] |
19487 |
1 |
|
|
T3 |
16 |
|
T4 |
307 |
|
T36 |
6 |
higher_val |
zero_val |
auto[0] |
80 |
1 |
|
|
T22 |
1 |
|
T195 |
1 |
|
T23 |
1 |
higher_val |
zero_val |
auto[1] |
38626 |
1 |
|
|
T3 |
26 |
|
T4 |
593 |
|
T36 |
10 |
lower_val |
higher_val |
auto[0] |
47065 |
1 |
|
|
T1 |
49 |
|
T5 |
7 |
|
T6 |
37 |
lower_val |
higher_val |
auto[1] |
19052 |
1 |
|
|
T3 |
15 |
|
T4 |
326 |
|
T36 |
13 |
lower_val |
lower_val |
auto[0] |
47021 |
1 |
|
|
T1 |
45 |
|
T5 |
14 |
|
T6 |
51 |
lower_val |
lower_val |
auto[1] |
19254 |
1 |
|
|
T3 |
18 |
|
T4 |
310 |
|
T36 |
12 |
lower_val |
zero_val |
auto[0] |
76 |
1 |
|
|
T196 |
1 |
|
T54 |
1 |
|
T62 |
1 |
lower_val |
zero_val |
auto[1] |
37983 |
1 |
|
|
T3 |
43 |
|
T4 |
594 |
|
T36 |
15 |
zero_val |
higher_val |
auto[0] |
608 |
1 |
|
|
T1 |
1 |
|
T6 |
1 |
|
T11 |
1 |
zero_val |
higher_val |
auto[1] |
129 |
1 |
|
|
T19 |
1 |
|
T195 |
1 |
|
T54 |
2 |
zero_val |
lower_val |
auto[0] |
593 |
1 |
|
|
T2 |
2 |
|
T5 |
1 |
|
T61 |
1 |
zero_val |
lower_val |
auto[1] |
142 |
1 |
|
|
T4 |
1 |
|
T36 |
1 |
|
T19 |
1 |
zero_val |
zero_val |
auto[0] |
253 |
1 |
|
|
T3 |
1 |
|
T4 |
1 |
|
T36 |
1 |
zero_val |
zero_val |
auto[1] |
158 |
1 |
|
|
T4 |
1 |
|
T195 |
7 |
|
T8 |
1 |