Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
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Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 0 15 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
msg_len 15 0 15 100.00 100 1 1 0


Summary for Variable msg_len

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for msg_len

Excluded/Illegal bins
NAMECOUNTSTATUS
remainder 10122 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
len_7501_10000 9146 1 T1 32 T3 28 T4 38
len_5001_7500 14990 1 T1 69 T3 59 T4 36
len_2501_5000 9296 1 T1 17 T3 9 T4 36
len_1025_2500 5388 1 T1 9 T3 7 T4 22
len_769_1024 6550 1 T1 1 T4 4 T6 2
len_513_768 6992 1 T1 1 T3 2 T4 4
len_257_512 21179 1 T1 1 T4 52 T6 2
len_0_256 252623 1 T1 14 T3 17 T4 2017
len_keccak_block_sizes[72] 703 1 T4 3 T36 1 T19 3
len_keccak_block_sizes[104] 615 1 T4 3 T19 3 T77 2
len_keccak_block_sizes[136] 513 1 T4 3 T19 3 T77 2
len_keccak_block_sizes[144] 410 1 T4 3 T19 3 T78 2
len_keccak_block_sizes[168] 318 1 T4 3 T19 3 T197 3
len_1 751 1 T4 3 T19 3 T77 2
len_0 1241 1 T1 5 T3 2 T4 3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%