Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100157803	1			T1	229654		T3	1917		T4	456139
all_pins[1]	100157803	1			T1	229654		T3	1917		T4	456139
all_pins[2]	100157803	1			T1	229654		T3	1917		T4	456139

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299590599	1			T1	688747		T3	5568		T4	136499
values[0x1]	882810	1			T1	215		T3	183		T4	3424
transitions[0x0=>0x1]	880182	1			T1	215		T3	183		T4	3424
transitions[0x1=>0x0]	880203	1			T1	215		T3	183		T4	3424

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99655423	1			T1	229439		T3	1742		T4	452715
all_pins[0]	values[0x1]	502380	1			T1	215		T3	175		T4	3424
all_pins[0]	transitions[0x0=>0x1]	502371	1			T1	215		T3	175		T4	3424
all_pins[0]	transitions[0x1=>0x0]	6421	1			T3	8		T6	89		T58	53
all_pins[1]	values[0x0]	100151373	1			T1	229654		T3	1909		T4	456139
all_pins[1]	values[0x1]	6430	1			T3	8		T6	89		T58	53
all_pins[1]	transitions[0x0=>0x1]	6110	1			T3	8		T6	89		T58	53
all_pins[1]	transitions[0x1=>0x0]	373680	1			T14	1247		T95	517		T80	338
all_pins[2]	values[0x0]	99783803	1			T1	229654		T3	1917		T4	456139
all_pins[2]	values[0x1]	374000	1			T14	1247		T95	517		T80	338
all_pins[2]	transitions[0x0=>0x1]	371701	1			T14	1247		T95	517		T80	338
all_pins[2]	transitions[0x1=>0x0]	500102	1			T1	215		T3	175		T4	3424