Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
11049476 |
1 |
|
|
T1 |
23500 |
|
T3 |
20844 |
|
T4 |
47900 |
auto[1] |
11049368 |
1 |
|
|
T1 |
23500 |
|
T3 |
20844 |
|
T4 |
47900 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
21861426 |
1 |
|
|
T1 |
46774 |
|
T3 |
41510 |
|
T4 |
93928 |
triple_byte_access |
78954 |
1 |
|
|
T1 |
80 |
|
T3 |
58 |
|
T4 |
620 |
halfword_access |
79418 |
1 |
|
|
T1 |
76 |
|
T3 |
64 |
|
T4 |
632 |
byte_access |
79046 |
1 |
|
|
T1 |
70 |
|
T3 |
56 |
|
T4 |
620 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10930767 |
1 |
|
|
T1 |
23387 |
|
T3 |
20755 |
|
T4 |
46964 |
auto[0] |
triple_byte_access |
39477 |
1 |
|
|
T1 |
40 |
|
T3 |
29 |
|
T4 |
310 |
auto[0] |
halfword_access |
39709 |
1 |
|
|
T1 |
38 |
|
T3 |
32 |
|
T4 |
316 |
auto[0] |
byte_access |
39523 |
1 |
|
|
T1 |
35 |
|
T3 |
28 |
|
T4 |
310 |
auto[1] |
word_access |
10930659 |
1 |
|
|
T1 |
23387 |
|
T3 |
20755 |
|
T4 |
46964 |
auto[1] |
triple_byte_access |
39477 |
1 |
|
|
T1 |
40 |
|
T3 |
29 |
|
T4 |
310 |
auto[1] |
halfword_access |
39709 |
1 |
|
|
T1 |
38 |
|
T3 |
32 |
|
T4 |
316 |
auto[1] |
byte_access |
39523 |
1 |
|
|
T1 |
35 |
|
T3 |
28 |
|
T4 |
310 |