Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99969248	1			T1	272		T2	550940		T3	3287
all_values[1]	99969248	1			T1	272		T2	550940		T3	3287
all_values[2]	99969248	1			T1	272		T2	550940		T3	3287

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

593391

1

T1

12

T2

7

T3

109

auto[1]

299314353

1

T1

804

T2

165281

T3

9752

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

298374981

1

T1

771

T2

164227

T3

8928

auto[1]

1532763

1

T1

45

T2

10542

T3

933

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	205985	1			T2	3		T3	65		T4	233
all_values[0]	auto[0]	auto[1]	2271	1			T2	4		T3	8		T4	4
all_values[0]	auto[1]	auto[0]	99252342	1			T1	257		T2	547423		T3	2911
all_values[0]	auto[1]	auto[1]	508650	1			T1	15		T2	3510		T3	303
all_values[1]	auto[0]	auto[0]	168742	1			T1	5		T3	32		T4	2639
all_values[1]	auto[0]	auto[1]	1644	1			T1	1		T3	4		T4	14
all_values[1]	auto[1]	auto[0]	99289585	1			T1	252		T2	547426		T3	2944
all_values[1]	auto[1]	auto[1]	509277	1			T1	14		T2	3514		T3	307
all_values[2]	auto[0]	auto[0]	213084	1			T1	5		T4	5074		T7	5
all_values[2]	auto[0]	auto[1]	1665	1			T1	1		T4	5		T7	2
all_values[2]	auto[1]	auto[0]	99245243	1			T1	252		T2	547426		T3	2976
all_values[2]	auto[1]	auto[1]	509256	1			T1	14		T2	3514		T3	311