Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
367244 |
1 |
|
|
T1 |
18 |
|
T2 |
4674 |
|
T3 |
396 |
auto[1] |
327014 |
1 |
|
|
T4 |
212 |
|
T8 |
16 |
|
T9 |
180 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173518 |
1 |
|
|
T1 |
5 |
|
T2 |
1150 |
|
T3 |
104 |
lower_val |
173239 |
1 |
|
|
T1 |
6 |
|
T2 |
1272 |
|
T3 |
83 |
zero_val |
1952 |
1 |
|
|
T1 |
1 |
|
T2 |
11 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
264696 |
1 |
|
|
T1 |
10 |
|
T2 |
2278 |
|
T3 |
202 |
lower_val |
266122 |
1 |
|
|
T1 |
8 |
|
T2 |
2396 |
|
T3 |
194 |
zero_val |
163440 |
1 |
|
|
T4 |
76 |
|
T8 |
8 |
|
T9 |
96 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
45827 |
1 |
|
|
T1 |
5 |
|
T2 |
556 |
|
T3 |
50 |
higher_val |
higher_val |
auto[1] |
20459 |
1 |
|
|
T4 |
14 |
|
T8 |
1 |
|
T9 |
7 |
higher_val |
lower_val |
auto[0] |
45454 |
1 |
|
|
T2 |
594 |
|
T3 |
54 |
|
T4 |
13 |
higher_val |
lower_val |
auto[1] |
20651 |
1 |
|
|
T4 |
20 |
|
T8 |
1 |
|
T9 |
13 |
higher_val |
zero_val |
auto[0] |
93 |
1 |
|
|
T10 |
1 |
|
T11 |
1 |
|
T12 |
1 |
higher_val |
zero_val |
auto[1] |
41034 |
1 |
|
|
T4 |
17 |
|
T9 |
22 |
|
T10 |
45 |
lower_val |
higher_val |
auto[0] |
45629 |
1 |
|
|
T1 |
2 |
|
T2 |
626 |
|
T3 |
43 |
lower_val |
higher_val |
auto[1] |
20308 |
1 |
|
|
T4 |
21 |
|
T8 |
3 |
|
T9 |
7 |
lower_val |
lower_val |
auto[0] |
46005 |
1 |
|
|
T1 |
4 |
|
T2 |
646 |
|
T3 |
40 |
lower_val |
lower_val |
auto[1] |
20671 |
1 |
|
|
T4 |
25 |
|
T8 |
2 |
|
T9 |
15 |
lower_val |
zero_val |
auto[0] |
78 |
1 |
|
|
T11 |
2 |
|
T13 |
1 |
|
T37 |
1 |
lower_val |
zero_val |
auto[1] |
40548 |
1 |
|
|
T4 |
28 |
|
T8 |
4 |
|
T9 |
27 |
zero_val |
higher_val |
auto[0] |
570 |
1 |
|
|
T2 |
4 |
|
T3 |
1 |
|
T4 |
3 |
zero_val |
higher_val |
auto[1] |
166 |
1 |
|
|
T11 |
1 |
|
T36 |
1 |
|
T37 |
1 |
zero_val |
lower_val |
auto[0] |
624 |
1 |
|
|
T1 |
1 |
|
T2 |
7 |
|
T5 |
1 |
zero_val |
lower_val |
auto[1] |
140 |
1 |
|
|
T4 |
2 |
|
T11 |
1 |
|
T36 |
2 |
zero_val |
zero_val |
auto[0] |
259 |
1 |
|
|
T4 |
1 |
|
T10 |
1 |
|
T11 |
2 |
zero_val |
zero_val |
auto[1] |
193 |
1 |
|
|
T6 |
2 |
|
T11 |
1 |
|
T13 |
1 |