Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10352	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8826	1			T2	30		T3	48		T4	6
len_5001_7500	14153	1			T2	30		T3	99		T4	11
len_2501_5000	9247	1			T2	30		T3	21		T4	2
len_1025_2500	5345	1			T2	16		T3	6		T4	3
len_769_1024	6093	1			T2	4		T3	5		T4	22
len_513_768	6537	1			T2	2		T3	1		T4	27
len_257_512	21039	1			T2	244		T3	3		T4	25
len_0_256	258711	1			T1	9		T2	1897		T3	15
len_keccak_block_sizes[72]	724	1			T2	3		T7	2		T38	2
len_keccak_block_sizes[104]	628	1			T2	3		T6	1		T11	1
len_keccak_block_sizes[136]	523	1			T2	3		T6	1		T26	1
len_keccak_block_sizes[144]	416	1			T2	3		T36	1		T181	3
len_keccak_block_sizes[168]	313	1			T2	3		T181	3		T182	3
len_1	763	1			T2	3		T7	2		T11	1
len_0	1206	1			T2	3		T3	2		T7	2