Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99969248	1			T1	272		T2	550940		T3	3287
all_pins[1]	99969248	1			T1	272		T2	550940		T3	3287
all_pins[2]	99969248	1			T1	272		T2	550940		T3	3287

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299080416	1			T1	801		T2	164931		T3	9558
values[0x1]	827328	1			T1	15		T2	3510		T3	303
transitions[0x0=>0x1]	825078	1			T1	15		T2	3510		T3	303
transitions[0x1=>0x0]	825097	1			T1	15		T2	3510		T3	303

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99460598	1			T1	257		T2	547430		T3	2984
all_pins[0]	values[0x1]	508650	1			T1	15		T2	3510		T3	303
all_pins[0]	transitions[0x0=>0x1]	508636	1			T1	15		T2	3510		T3	303
all_pins[0]	transitions[0x1=>0x0]	5164	1			T4	40		T5	3		T8	1
all_pins[1]	values[0x0]	99964070	1			T1	272		T2	550940		T3	3287
all_pins[1]	values[0x1]	5178	1			T4	40		T5	3		T8	1
all_pins[1]	transitions[0x0=>0x1]	4854	1			T4	24		T5	3		T8	1
all_pins[1]	transitions[0x1=>0x0]	313176	1			T4	4961		T11	7993		T36	394
all_pins[2]	values[0x0]	99655748	1			T1	272		T2	550940		T3	3287
all_pins[2]	values[0x1]	313500	1			T4	4977		T11	7993		T36	394
all_pins[2]	transitions[0x0=>0x1]	311588	1			T4	4941		T11	7941		T36	390
all_pins[2]	transitions[0x1=>0x0]	506757	1			T1	15		T2	3510		T3	303