Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10589688 |
1 |
|
|
T1 |
96 |
|
T2 |
27235 |
|
T3 |
32387 |
auto[1] |
10589677 |
1 |
|
|
T1 |
96 |
|
T2 |
27235 |
|
T3 |
32387 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
20941901 |
1 |
|
|
T1 |
192 |
|
T2 |
52796 |
|
T3 |
64470 |
triple_byte_access |
79288 |
1 |
|
|
T2 |
558 |
|
T3 |
124 |
|
T4 |
54 |
halfword_access |
79610 |
1 |
|
|
T2 |
558 |
|
T3 |
98 |
|
T4 |
56 |
byte_access |
78566 |
1 |
|
|
T2 |
558 |
|
T3 |
82 |
|
T4 |
60 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
0 |
8 |
100.00 |
|
Automatically Generated Cross Bins for state_mask_share_cross
Bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10470956 |
1 |
|
|
T1 |
96 |
|
T2 |
26398 |
|
T3 |
32235 |
auto[0] |
triple_byte_access |
39644 |
1 |
|
|
T2 |
279 |
|
T3 |
62 |
|
T4 |
27 |
auto[0] |
halfword_access |
39805 |
1 |
|
|
T2 |
279 |
|
T3 |
49 |
|
T4 |
28 |
auto[0] |
byte_access |
39283 |
1 |
|
|
T2 |
279 |
|
T3 |
41 |
|
T4 |
30 |
auto[1] |
word_access |
10470945 |
1 |
|
|
T1 |
96 |
|
T2 |
26398 |
|
T3 |
32235 |
auto[1] |
triple_byte_access |
39644 |
1 |
|
|
T2 |
279 |
|
T3 |
62 |
|
T4 |
27 |
auto[1] |
halfword_access |
39805 |
1 |
|
|
T2 |
279 |
|
T3 |
49 |
|
T4 |
28 |
auto[1] |
byte_access |
39283 |
1 |
|
|
T2 |
279 |
|
T3 |
41 |
|
T4 |
30 |