Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99060203	1			T1	4		T2	303		T3	162173
all_values[1]	99060203	1			T1	4		T2	303		T3	162173
all_values[2]	99060203	1			T1	4		T2	303		T3	162173

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

497221

1

T1

8

T2

6

T3

19

auto[1]

296683388

1

T1

4

T2

903

T3

486500

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

295664349

1

T1

12

T2

867

T3

485121

auto[1]

1516260

1

T2

42

T3

1398

T4

42

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	179587	1			T3	6		T4	4		T11	65
all_values[0]	auto[0]	auto[1]	2131	1			T3	6		T4	2		T11	8
all_values[0]	auto[1]	auto[0]	98375196	1			T1	4		T2	289		T3	161701
all_values[0]	auto[1]	auto[1]	503289	1			T2	14		T3	460		T4	12
all_values[1]	auto[0]	auto[0]	177796	1			T1	4		T3	3		T5	2354
all_values[1]	auto[0]	auto[1]	1673	1			T3	4		T5	1		T13	12
all_values[1]	auto[1]	auto[0]	98376987	1			T2	289		T3	161704		T4	278
all_values[1]	auto[1]	auto[1]	503747	1			T2	14		T3	462		T4	14
all_values[2]	auto[0]	auto[0]	134498	1			T1	4		T2	5		T10	6
all_values[2]	auto[0]	auto[1]	1536	1			T2	1		T10	5		T61	4
all_values[2]	auto[1]	auto[0]	98420285	1			T2	284		T3	161707		T4	278
all_values[2]	auto[1]	auto[1]	503884	1			T2	13		T3	466		T4	14