Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
366350 |
1 |
|
|
T1 |
2 |
|
T2 |
18 |
|
T3 |
620 |
auto[1] |
320716 |
1 |
|
|
T4 |
16 |
|
T10 |
618 |
|
T5 |
220 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173144 |
1 |
|
|
T1 |
1 |
|
T2 |
6 |
|
T3 |
146 |
lower_val |
169608 |
1 |
|
|
T2 |
2 |
|
T3 |
142 |
|
T4 |
3 |
zero_val |
1899 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
263236 |
1 |
|
|
T2 |
8 |
|
T3 |
306 |
|
T4 |
4 |
lower_val |
263096 |
1 |
|
|
T2 |
10 |
|
T3 |
314 |
|
T4 |
6 |
zero_val |
160734 |
1 |
|
|
T1 |
2 |
|
T4 |
8 |
|
T10 |
284 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
0 |
18 |
100.00 |
|
Automatically Generated Cross Bins for entropy_timer_cross
Bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
46131 |
1 |
|
|
T2 |
3 |
|
T3 |
66 |
|
T11 |
2 |
higher_val |
higher_val |
auto[1] |
20406 |
1 |
|
|
T4 |
1 |
|
T10 |
41 |
|
T5 |
10 |
higher_val |
lower_val |
auto[0] |
45987 |
1 |
|
|
T2 |
3 |
|
T3 |
80 |
|
T11 |
2 |
higher_val |
lower_val |
auto[1] |
20099 |
1 |
|
|
T4 |
1 |
|
T10 |
39 |
|
T5 |
22 |
higher_val |
zero_val |
auto[0] |
90 |
1 |
|
|
T1 |
1 |
|
T104 |
1 |
|
T50 |
1 |
higher_val |
zero_val |
auto[1] |
40431 |
1 |
|
|
T4 |
2 |
|
T10 |
70 |
|
T5 |
32 |
lower_val |
higher_val |
auto[0] |
45117 |
1 |
|
|
T2 |
1 |
|
T3 |
69 |
|
T14 |
84 |
lower_val |
higher_val |
auto[1] |
20008 |
1 |
|
|
T10 |
39 |
|
T5 |
9 |
|
T13 |
231 |
lower_val |
lower_val |
auto[0] |
45060 |
1 |
|
|
T2 |
1 |
|
T3 |
73 |
|
T10 |
1 |
lower_val |
lower_val |
auto[1] |
19840 |
1 |
|
|
T4 |
2 |
|
T10 |
54 |
|
T5 |
10 |
lower_val |
zero_val |
auto[0] |
90 |
1 |
|
|
T9 |
1 |
|
T35 |
1 |
|
T31 |
1 |
lower_val |
zero_val |
auto[1] |
39493 |
1 |
|
|
T4 |
1 |
|
T10 |
71 |
|
T5 |
27 |
zero_val |
higher_val |
auto[0] |
552 |
1 |
|
|
T3 |
1 |
|
T13 |
1 |
|
T62 |
1 |
zero_val |
higher_val |
auto[1] |
149 |
1 |
|
|
T13 |
2 |
|
T107 |
3 |
|
T211 |
1 |
zero_val |
lower_val |
auto[0] |
590 |
1 |
|
|
T2 |
1 |
|
T3 |
2 |
|
T10 |
1 |
zero_val |
lower_val |
auto[1] |
152 |
1 |
|
|
T13 |
2 |
|
T106 |
2 |
|
T107 |
1 |
zero_val |
zero_val |
auto[0] |
254 |
1 |
|
|
T1 |
1 |
|
T4 |
1 |
|
T5 |
1 |
zero_val |
zero_val |
auto[1] |
202 |
1 |
|
|
T13 |
4 |
|
T106 |
2 |
|
T107 |
2 |