Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	10182	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	8978	1			T3	24		T10	24		T5	30
len_5001_7500	14402	1			T3	24		T10	24		T5	55
len_2501_5000	9154	1			T3	24		T10	24		T5	8
len_1025_2500	5384	1			T3	14		T10	14		T5	6
len_769_1024	6188	1			T3	2		T10	2		T5	1
len_513_768	6499	1			T3	3		T10	3		T5	1
len_257_512	20429	1			T3	2		T10	2		T5	2
len_0_256	255224	1			T2	9		T3	211		T4	9
len_keccak_block_sizes[72]	712	1			T3	2		T10	2		T13	3
len_keccak_block_sizes[104]	611	1			T3	2		T10	2		T13	3
len_keccak_block_sizes[136]	518	1			T13	3		T61	2		T80	3
len_keccak_block_sizes[144]	420	1			T13	3		T80	3		T83	2
len_keccak_block_sizes[168]	316	1			T13	3		T80	3		T107	3
len_1	753	1			T3	2		T10	2		T13	3
len_0	1236	1			T3	2		T10	2		T5	3